Zilog Z86193 - Manual (Page 142)

Z8
®
CPU
User Manual
UM001604-0108 External Interface
135
clock is shown for clarity only and does not have a specific timing relationship with other
signals.
Figure 126. External Instruction Fetch or Memory Read Cycle
Machine Cycle
T1 T2* T3
Clock
A15-A8
AD7–AD0
AS
DS
R/W
DM
Read Cycle
A8-A15
A7–A0 D7–D0 IN
*Port inputs are strobed during T2, which is two internal systems clocks
before the execution cycle of the current instruction.