Zilog Z86193 - Manual (Page 133)

Z8
®
CPU
User Manual
UM001604-0108 Serial Input/Output
126
sion of the internal system clock if this is used as the SPI clock source. Divide by 2, 4, 8,
or 16 is chosen as the scaler.
Receive Character Available and Overrun
When a complete data stream is received, an interrupt is generated and the RxCharAvail
bit in the SCON Register is set. Bit 4 in the SCON Register is for enabling or disabling the
RxCharAvail interrupt. The RxCharAvail bit is available for interrupt polling purposes and
is reset when the RxBUF Register is read. RxCharAvail is generated in both master and
Figure 117. SPI System Configuration
ss sk do di
Slave
Multiple slaves may have the same address
ss1
ss4
do
ss2
ss3
sk
di
Master
Three Wire Compare Setup
ss sk do di
Slave ss sk do di
Slave ss sk do di
Slave
ss
sk
do
di
Master
ss sk do di
Slave
Setup For Compare
ss sk do di
Slave ss sk do di
Slave ss sk do di
Slave
ss
sk
do
di
Master
Up to 256 slaves per SS line
(1) (2) (255) (256)
ss sk do di
Slave ss sk do di
Slave ss sk do di
Slave ss sk do di
Slave
Standard Parallel Setup
ss sk do di
Slave
Standard Serial Setup
ss sk do di
Slave ss sk do di
Slave
ss sk do di
Slave
ss
sk
do
di
Master