Internal interrupt sources, Interrupt request register logic and timing – Zilog Z86193 User Manual

Page 105

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UM001604-0108

Interrupts

IRQ3 can be generated from an external source only if Serial In is not enabled. Otherwise,
its source is internal. The external request is generated by a Low edge signal on P30 as dis-
played in

Figure 93

. Again, the external request is synchronized and delayed before reach-

ing IRQ3. Some Z8 products replace P30 with P32 as the external source for IRQ3. In this
case, IRQ3 interrupt generation follows the logic as displayed in

Figure 92

on page 97.

Although interrupts are edge triggered, minimum interrupt request Low and High times
must be observed for proper operation. See the device product specification for exact tim-
ing requirements on external interrupt requests (T

IL, T

IH).

Internal Interrupt Sources

Internal sources involve interrupt requests IRQ0, IRQ2, IRQ3, IRQ4, and IRQ5. Internal
sources are ORed with the external sources, so either an internal or external source can
trigger the interrupt. Internal interrupt sources and trigger conditions are device depen-
dent.

Refer to the device product specification to determine available sources, triggering edge
options, and exact programming details. For more details on the internal interrupt sources,
see Counters and Timers, Input/Output Ports, and Serial Input/Output sections.

Interrupt Request Register Logic and Timing

Figure 94

displays the logic diagram for the Interrupt Request (IRQ) Register. The leading

edge of the request sets the first flip-flop, that remains set until interrupt requests are sam-
pled.

Requests are sampled internally during the last clock cycle before an opcode fetch (see

Figure 95

). External requests are sampled two internal clocks earlier, due to the synchro-

nizing flip-flops as displayed in

Figure 92

on page 97

and

Figure 93