Avago Technologies LSI53C895A - Manual (Page 110)

4-2 Registers
not supported are not writable and return all zeros when read. Only those
registers and bits that are currently supported by the LSI53C895A are
described in this chapter. Reserved bits should not be accessed
.
Table 4.1 PCI Configuration Register Map
31 16 15 0
Device ID Vendor ID 0x00
Status Command 0x04
Class Code Revision ID (Rev ID) 0x08
Not Supported Header Type Latency Timer Cache Line Size 0x0C
Base Address Register Zero (I/O) 0x10
Base Address Register One (MEMORY) bits [31:0] 0x14
Base Address Register Two (SCRIPTS RAM) 0x18
Not Supported 0x1C
Not Supported 0x20
Not Supported 0x24
Reserved 0x28
Subsystem ID Subsystem Vendor ID 0x2C
Expansion ROM Base Address 0x30
Reserved Capabilities Pointer 0x34
Reserved 0x38
Max_Lat Min_Gnt Interrupt Pin Interrupt Line 0x3C
Power Management Capabilities (PMC) Next Item Pointer Capability ID 0x40
Data
Bridge Support Exten-
sions (PMCSR_BSE)
Power Management Control/Status (PMCSR) 0x44
Subsystem ID Access 0x48