Avago Technologies LSI53C895A - Manual (Page 13)

Contents xiii
3.14 Power and Ground Signals 3-17
3.15 Decode of MAD Pins 3-20
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Address Map 4-20
4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1
4-33
4.4 Example Transfer Periods and Rates for Fast SCSI-2,
Ultra, and Ultra2
4-34
4.5 Maximum Synchronous Offset 4-35
4.6 SCSI Synchronous Data FIFO Word Count 4-45
5.1 SCRIPTS Instructions 5-3
5.2 SCSI Information Transfer Phase 5-11
5.3 Read/Write Instructions 5-24
5.4 Transfer Control Instructions 5-26
5.5 SCSI Phase Comparisons 5-29
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 LVD Driver SCSI Signals—SD[15:0]+, SDP[1:0]/, SREQ/,
SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/, SATN/,
SBSY/, SSEL/, SRST/
6-3
6.4 LVD Receiver SCSI Signals—SD[15:0]/, SDP[1:0]/,
SREQ/, SREQ2/, SACK/, SACK2/, SMSG/, SIO/, SCD/,
SATN/, SBSY/, SSEL/, SRST/
6-3
6.5 DIFFSENS SCSI Signal 6-4
6.6 Input Capacitance 6-4
6.7 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/,
MOE/, MWE/
6-5
6.8 Bidirectional Signals—GPIO0_FETCH/,
GPIO1_MASTER/, GPIO[2:8]
6-5
6.9 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR
6-6
6.10 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK,
TDI, TEST_HSC, TEST_RST, TMS, TRST/
6-6
6.11 Output Signal—TDO 6-7
6.12 Output Signals—ALT_IRQ/, IRQ/, MAC/_TESTOUT,
REQ/
6-7
6.13 Output Signal—SERR/ 6-7
6.14 TolerANT Technology Electrical Characteristics for SE
SCSI Signals
6-8