Avago Technologies LSI53C895A User Manual
Page 322
6-62
Electrical Specifications
Table 6.49
Ultra SCSI High Voltage Differential Transfers 20.0 Mbytes (8-Bit Transfers)
or 40.0 Mbytes (16-Bit Transfers) 80 MHz Clock
1, 2
1. Transfer period bits (bits [7:5] in the
register) are set to zero and the Extra
Clock Cycle of Data Setup bit (bit 7 in
) is set.
2. During Ultra SCSI transfers, the value of the Extend REQ/ACK Filtering bit (
, bit 1) has no effect.
Symbol
Parameter
Min
Max
Unit
t
1
Send SREQ/ or SACK/ assertion pulse width
15
–
ns
t
2
Send SREQ/ or SACK/ deassertion pulse width
15
–
ns
t
1
Receive SREQ/ or SACK/ assertion pulse width
11
–
ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width
11
–
ns
t
3
Send data setup to SREQ/ or SACK/ asserted
16
–
ns
t
4
Send data hold from SREQ/ or SACK/ asserted
21
–
ns
t
5
Receive data setup to SREQ/ or SACK/ asserted
6
–
ns
t
6
Receive data hold from SREQ/ or SACK/ asserted
11
–
ns