Avago Technologies LSI53C895A - Manual (Page 25)

LSI53C895A Benefits Summary 1-9
1.5.5 Flexibility
The LSI53C895A provides:
•
Universal LVD transceivers are backward compatible with SE or HVD
devices.
•
High level programming interface (SCSI SCRIPTS).
•
Ability to program local and bus flash memory.
•
Selectable 112 or 944 byte DMA FIFO for backward compatibility.
•
Tailored SCSI sequences execute from main system RAM or internal
SCRIPTS RAM.
•
Flexible programming interface to tune I/O performance or to adapt
to unique SCSI devices.
•
Support for changes in the logical I/O interface definition.
•
Low level access to all registers and all SCSI bus signals.
•
Fetch, Master, and Memory Access control pins.
•
Separate SCSI and system clocks.
•
SCSI clock quadrupler bits enable Ultra2 SCSI transfer rates with a
40 MHz SCSI clock input.
•
Selectable IRQ pin disable bit.
•
Ability to route system clock to SCSI clock.
•
Compatible with 3.3 V and 5 V PCI.
1.5.6 Reliability
Enhanced reliability features of the LSI53C895A include:
•
2 kV ESD protection on SCSI signals.
•
Protection against bus reflections due to impedance mismatches.
•
Controlled bus assertion times (reduces RFI, improves reliability, and
eases FCC certification).
•
Latch-up protection greater than 150 mA.
•
Voltage feed-through protection (minimum leakage current through
SCSI pads).
•
High proportion (> 25%) of device pins are power or ground.