Avago Technologies LSI53C895A User Manual
Page 181
SCSI Registers
4-73
IRQM
IRQ Mode
3
When set, this bit enables a totem pole driver for the IRQ/
pin. When cleared, this bit enables an open drain driver
for the IRQ/ pin with an internal weak pull-up. The bit
should remain cleared to retain full PCI compliance.
STD
Start DMA Operation
2
The LSI53C895A fetches a SCSI SCRIPTS instruction
from the address contained in the
register when this bit is set. This bit is required if
the LSI53C895A is in one of the following modes:
•
Manual start mode – Bit 0 in the
register is set
•
Single step mode – Bit 4 in the
register is set
When the LSI53C895A is executing SCRIPTS in manual
start mode, the Start DMA bit must be set to start
instruction fetches, but need not be set again until an
interrupt occurs. When the LSI53C895A is in single step
mode, set the Start DMA bit to restart execution of
SCRIPTS after a single step interrupt.
IRQD
IRQ Disable
1
Setting this bit disables the IRQ pin. Clearing the bit
enables normal operation. As with any other register
other than
Interrupt Status Zero (ISTAT0)
and
, this register cannot be accessed
except by a SCRIPTS instruction during SCRIPTS
execution. For more information on the use of this bit in
interrupt handling, see
COM
LSI53C700 Family Compatibility
0
When the COM bit is cleared, the LSI53C895A behaves
in a manner compatible with the LSI53C700 family;
selection/reselection IDs are stored in both the
and
SCSI First Byte Received (SFBR)
registers. This bit is not affected by a software reset.
If the COM bit is cleared, do not access this register
using SCRIPTS operation as nondeterminate operations
may occur. (This includes SCRIPTS Read/Write
operations and conditional transfer control instructions
that initialize the SFBR register.)