Avago Technologies LSI53C895A - Manual (Page 123)

PCI Configuration Registers 4-15
Register: 0x3F
Max_Lat
Read Only
ML MAX_LAT [7:0]
This register is used to specify the desired settings for
latency timer values. Max_Lat is used to specify how
often the device needs to gain access to the PCI bus.
The value specified in this register is in units of
0.25 microseconds. The LSI53C895A sets this register to
0x40.
Register: 0x40
Capability ID
Read Only
CID Cap_ID [7:0]
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure.
Register: 0x41
Next Item Pointer
Read Only
NIP Next_Item_Ptr [7:0]
Bits [7:0] contain the offset location of the next item in the
controller’s capabilities list. The LSI53C895A has these
bits set to zero indicating no further extended capabilities
registers exist.
7 0
ML
0 1 0 0 0 0 0 0
7 0
CID
0 0 0 0 0 0 0 1
7 0
NIP
0 0 0 0 0 0 0 0