Avago Technologies LSI53C895A - Manual (Page 275)

PCI and External Memory Interface Timing Diagrams 6-15
– 32-Bit Operating Register/SCRIPTS RAM Write
– 64-Bit Address Operating Register/SCRIPTS RAM Write
•
Initiator Timing
– Nonburst Opcode Fetch, 32-Bit Address and Data
– Burst Opcode Fetch, 32-Bit Address and Data
– Back to Back Read, 32-Bit Address and Data
– Back to Back Write, 32-Bit Address and Data
– Burst Read, 32-Bit Address and Data
– Burst Read, 64-Bit Address and Data
– Burst Write, 32-Bit Address and Data
– Burst Write, 64-Bit Address and 32-Bit Data
•
External Memory Timing
– External Memory Read
– External Memory Write
– Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Read
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access Write
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Read
Cycle
– Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Write
Cycle
– Slow Memory (
≤
128 Kbytes) Read Cycle
– Slow Memory (
≤
128 Kbytes) Write Cycle
–
≤
64 Kbytes ROM Read Cycle
–
≤
64 Kbyte ROM Write Cycle
6.4.1 Target Timing
Tables 6.17 through 6.23 and Figures 6.11 through 6.16 describe Target
timing.