Avago Technologies LSI53C895A - Manual (Page 200)

4-92 Registers
Note: Do not set this bit during normal operation, since it could
cause contention on the SCSI bus. It is included for
diagnostic purposes only.
ROF Reset SCSI Offset 6
Setting this bit clears any outstanding synchronous
SREQ/SACK offset. Set this bit if a SCSI gross error
condition occurs and to clear the offset when a
synchronous transfer does not complete successfully.
The bit automatically clears itself after resetting the
synchronous offset.
DIF HVD or SE/LVD 5
Setting this bit allows the LSI53C895A to interface to
external HVD transceivers. Clearing this bit enables SE
or LVD operation. Set this bit in the initialization routine if
the differential pair interface is used.
SLB SCSI Loopback Mode 4
Setting this bit allows the LSI53C895A to perform SCSI
loopback diagnostics. That is, it enables the SCSI core to
simultaneously perform as both the initiator and the
target.
SZM SCSI High Impedance Mode 3
Setting this bit places all the open drain 48 mA SCSI
drivers into a high impedance state. This is to allow
internal loopback mode operation without affecting the
SCSI bus.
AWS Always Wide SCSI 2
When this bit is set, all SCSI information transfers are
done in 16-bit wide mode. This includes data, message,
command, status and reserved phases. Normally,
deassert this bit since 16-bit wide message, command,
and status phases are not supported by the SCSI
specifications.
EXT Extend SREQ/SACK/ Filtering 1
LSI Logic TolerANT SCSI receiver technology includes a
special digital filter on the SREQ/ and SACK/ pins which
causes the disregarding of glitches on deasserting
edges. Setting this bit increases the filtering period from
30 ns to 60 ns on the deasserting edge of the SREQ/ and
SACK/ signals.