Avago Technologies LSI53C895A - Manual (Page 355)

Index IX-9
SCSI (Cont.)
interrupt status zero (SIST0) 4-77
interrupts 2-48
isolation mode (ISO) 4-90
longitudinal parity (SLPAR) 4-81
loopback mode 2-26
loopback mode (SLB) 4-92
low level mode (LOW) 4-93
LVDlink 2-34
mode (SMODE[1:0]) 4-96
MSG/ signal (MSG) 4-46
output control latch (SOCL) 4-38
output data latch (SODL) 4-97
parity control 2-28
parity error (PAR) 4-76
performance 1-6
phase 5-11 , 5-28
phase mismatch - initiator mode 4-74
reset condition (RST) 4-76
RST/ received (RST) 4-79
RST/ signal (RST) 4-44
SDP0/ parity signal (SDP0) 4-44
SDP1 signal (SDP1) 4-48
selected as ID (SSAID) 4-89
selector ID (SSID) 4-39
serial EEPROM access 2-57
signals 3-12
status one (SSTAT1) 4-44
status two (SSTAT2) 4-46
status zero (SSTAT0) 4-43
synchronous offset maximum (SOM) 4-90
synchronous offset zero (SOZ) 4-89
synchronous transfer period (TP[2:0]) 4-32
termination 2-38
test four (STEST4) 4-96
test one (STEST1) 4-90
test three (STEST3) 4-93
test two (STEST2) 4-91
test zero (STEST0) 4-89
timer one (STIME1) 4-87
timer zero (STIME0) 4-85
TolerANT technology 1-5
transfer (SXFER) 4-32
true end of process (TEOP) 4-56
Ultra2 SCSI 2-22
valid (VAL) 4-39
wide residue (SWIDE) 4-82
SCSI SCRIPTS operation 5-2
sample instruction 5-3
SCSI-1 transfers (differential 4.17 mbytes) 6-60
SCSI-2
fast transfers
10.0 Mbytes (8-bit transfers)
40 MHz clock 6-60
50 MHz clock 6-61
20.0 Mbytes (16-bit transfers)
40 MHz clock 6-60
50 MHz clock 6-61
SCTRL signals 3-13
SD[15:0]+- 3-12
SDP[1:0]+- 3-12
second dword 5-12 , 5-21 , 5-23 , 5-32 , 5-34 , 5-37
SEL 2-45
select 2-19
instruction 5-16
with ATN/ 5-19
with SATN/ on a start sequence (WATN) 4-23
selected (SEL) 4-75 , 4-78
selection or reselection time-out (STO) 4-77 , 4-80
selection response logic test (SLT) 4-89
selection time-out (SEL[3:0]) 4-86
semaphore (SEM) 4-50
serial EEPROM
data format 2-58
interface 2-57
SERR/ 3-8
SERR/ enable (SE) 4-4
set instruction 5-15 , 5-17
set/clear
carry 5-20
SACK/ 5-20
shadow register test mode (SRTM) 4-60
SI_O+- 3-13
SI_O/ status (I_O) 4-40
SID 2-58
SIDL
least significant byte full (ILF) 4-43
most significant byte full (ILF1) 4-46
SIEN0 2-45
SIEN1 2-45
signal names
and BGA position 6-66 , 6-67
by BGA position 6-66 , 6-67
signal process (SIGP) 4-49 , 4-55
signaled system error (SSE) 4-5
simple arbitration 4-21
single
address cycles 2-21
ended SCSI signals 6-8
step interrupt (SSI) 4-41 , 4-70
step mode (SSM) 4-72
SIP 2-44 , 2-47 , 2-48
SIST0 2-27 , 2-44 , 2-47 , 2-49
SIST1 2-44 , 2-47 , 2-49
slow ROM pin 3-20
SLPAR high byte enable (SLPHBEN) 4-28
SLPAR mode (SLPMD) 4-28
SMSG+- 3-13
SMSG/ status (MSG) 4-40
SODL
least significant byte full (OLF) 4-43
most significant byte full (OLF1) 4-47
register 2-53 , 2-54 , 2-55
SODR
least significant byte full (ORF) 4-43
most significant byte full (ORF1) 4-46
software reset (SRST) 4-49
source I/O memory enable (SIOM) 4-68
special cycle command 2-5
SREQ 2-48
SREQ+- 3-13
SREQ/ status (REQ) 4-40
SREQ2+- 3-13
SRST+- 3-13
SSEL+- 3-13
SSEL/ status (SEL) 4-40
SSTAT0 2-27
SSTAT1 2-27
stacked interrupts 2-47
start
address 5-12 , 5-21
DMA operation (STD) 4-73