Avago Technologies LSI53C895A - Manual (Page 124)

4-16 Registers
Registers: 0x42–0x43
Power Management Capabilities (PMC)
Read Only
PMES PME_Support [15:11]
Bits [15:11] define the power management states in
which the LSI53C895A will assert the PME pin. These
bits are all set to zero because the LSI53C895A does not
provide a PME signal.
D2S D2_Support 10
The LSI53C895A sets this bit to indicate support for
power management state D2.
D1S D1_Support 9
The LSI53C895A sets this bit to indicate support for
power management state D1.
R Reserved [8:6]
DSI Device Specific Initialization 5
This bit is cleared to indicate that the LSI53C895A
requires no special initialization before the generic class
device driver is able to use it.
APS Auxiliary Power Source 4
Because the LSI53C895A does not provide a PME
signal, this bit is cleared, indicating that no auxiliary
power source is required to support the PME signal in the
D3cold power management state.
PMEC PME Clock 3
Bit 3 is cleared because the LSI53C895A does not
provide a PME pin.
VER[2:0] Version [2:0]
These three bits are set to 010 to indicate that the
LSI53C895A complies with Revision 1.1 of the PCI Power
Management Interface Specification.
15 11 10 9 8 6 5 4 3 2 0
PMES D2S D1S R DSI APS PMEC VER[2:0]
0 0 0 0 0 1 1 x x x 0 0 0 0 1 0