Avago Technologies LSI53C895A - Manual (Page 276)

6-16 Electrical Specifications
Figure 6.11 PCI Configuration Register Read
Table 6.18 PCI Configuration Register Read
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
CLK
FRAME/
AD
(Driven by Master-Addr;
LSI53C895A-Data)
C_BE/
(Driven by Master )
PAR
(Driven by Master-Addr;
LSI53C895A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
IDSEL
(Driven by Master)
t
1
t
2
Data Out
Byte Enable
t
1
t
1
t
1
t
2
t
1
t
2
t
2
t
2
t
1
t
2
t
2
t3
t
3
t
3
t
3
Out In
Addr
In
(Driven by System)
(Driven by System)
CMD