Avago Technologies LSI53C895A User Manual
Page 250
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SCSI SCRIPTS Instruction Set
When a Return instruction is executed, the value stored
in the
register is returned to the DSP
register. The LSI53C895A does not check to see whether
the Call instruction has already been executed. It does
not generate an interrupt if a Return instruction is
executed without previously executing a Call instruction.
If the comparisons are false, the LSI53C895A fetches the
next instruction from the address pointed to by the DSP
register and the instruction pointer is not modified.
Interrupt Instruction
The LSI53C895A can do a true/false comparison of the
ALU carry bit, or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields.
If the comparisons are true, the LSI53C895A generates
an interrupt by asserting the IRQ/ signal.
The 32-bit address field stored in the
register can contain a unique
interrupt service vector. When servicing the interrupt, this
unique status code allows the Interrupt Service Routine
to quickly identify the point at which the interrupt
occurred.
The LSI53C895A halts and the
register must be written to before starting any
further operation.
Interrupt-on-the-Fly Instruction
The LSI53C895A can do a true/false comparison of the
ALU carry bit or compare the phase and/or data as
defined by the Phase Compare, Data Compare, and
True/False bit fields. If the comparisons are true, and the
Interrupt-on-the-Fly bit (
Interrupt Status One (ISTAT1),
bit 2) is set, the LSI53C895A asserts the Interrupt-on-the-
Fly bit.
SCSIP[2:0]
SCSI Phase
[26:24]
This 3-bit field corresponds to the three SCSI bus phase
signals that are compared with the phase lines latched
when SREQ/ is asserted. Comparisons can be performed
to determine the SCSI phase actually being driven on the
SCSI bus.
describes the possible combinations
and their corresponding SCSI phase. These bits are only