Avago Technologies LSI53C895A - Manual (Page 81)

Parallel ROM Interface 2-55
transferred from memory but not to the SCSI bus when a partial transfer
exists. For example, if the instruction is an Initiator chained Block Move
Data Out of five bytes (and WSS is not previously set), five bytes are
transferred out of memory to the SCSI controller, four bytes are
transferred from the SCSI controller across the SCSI bus, and one byte
is temporarily stored in the lower byte of the
SCSI Output Data Latch
(SODL) register waiting to be married with the first byte of the next Block
Move instruction. Regardless of whether a chained Block Move or normal
Block Move instruction is used, if the WSS bit is set at the start of a data
send command, the first byte of the data send command is assumed to
be the high-order byte and is “married” with the low-order byte stored in
the lower byte of the
SCSI Output Data Latch (SODL) register before the
two bytes are sent across the SCSI bus. For “N” consecutive wide data
send Block Move commands, the first through the (N
th
– 1) Block Move
instructions should be Chained Block Moves.
2.3 Parallel ROM Interface
The LSI53C895A supports up to one megabyte of external memory in
binary increments from 16 Kbytes, to allow the use of expansion ROM
for add-in PCI cards. This interface is designed for low speed operations
such as downloading instruction code from ROM; it is not intended for
dynamic activities such as executing instructions.
System requirements include the LSI53C895A, two or three external
8-bit address holding registers (HCT273 or HCT374), and the
appropriate memory device. The 4.7 k
Ω
pull-up resistors on the MAD bus
require HC or HCT external components to be used. If in-system Flash
ROM updates are required, a 7406 (high voltage open collector inverter),
a MTD4P05, and several passive components are also needed. The
memory size and speed is determined by pull-up resistors on the
8-bit bidirectional memory bus at power-up. The LSI53C895A senses this
bus shortly after the release of the Reset signal and configures the
Expansion ROM Base Address register and the memory cycle state
machines for the appropriate conditions.
The external memory interface works with a variety of ROM sizes and
speeds. An example set of interface drawings is in
Appendix B, “External
Memory Interface Diagram Examples.”