Avago Technologies LSI53C895A - Manual (Page 95)

PCI Bus Interface Signals 3-7
IRDY/ 22 W9 S/T/S 8 mA PCI Initiator Ready indicates the
initiating agent’s (bus master’s)
ability to complete the current data
phase of the transaction. IRDY/ is
used with TRDY/. A data phase is
completed on any clock when both
IRDY/ and TRDY/ are sampled
asserted. During a write, IRDY/
indicates that valid data is present
on AD[31:0]. During a read, it
indicates that the master is
prepared to accept data. Wait cycles
are inserted until both IRDY/ and
TRDY/ are asserted together.
STOP/ 27 W11 S/T/S 8 mA PCI Stop indicates that the selected
target is requesting the master to
stop the current transaction.
DEVSEL/ 25 Y10 S/T/S 8 mA PCI Device Select indicates that the
driving device has decoded its
address as the target of the current
access. As an input, it indicates to a
master whether any device on the
bus has been selected.
IDSEL 9 V6 I N/A Initialization Device Select is used
as a chip select in place of the
upper 24 address lines during
configuration read and write
transactions.
Table 3.4 Interface Control Signals (Cont.)
Name PQFP BGA Pos Type Strength Description