Avago Technologies LSI53C896 - Manual (Page 126)

4-14 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x34
Capabilities Pointer
Read Only
CP Capabilities Pointer [7:0]
This register indicates that the first extended capability
register is located at offset 0x40 in the PCI Configuration.
Registers: 0x35–0x3B
Reserved
Register: 0x3C
Interrupt Line
Read/Write
IL Interrupt Line [7:0]
This register communicates interrupt line routing
information. POST software writes the routing information
into this register as it configures the system. The value in
this register tells which input of the system interrupt
controller(s) the device’s interrupt pin is connected to.
Values in this register are specified by system architecture.
7 0
CP
0 1 0 0 0 0 0 0
7 0
IL
0 0 0 0 0 0 0 0