Avago Technologies LSI53C896 - Manual (Page 332)

6-64 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table 6.45 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 35 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 35 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 20 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 20 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 33 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 45 – ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 0 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 10 – ns
Table 6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 50 MHz Clock
1
1. Transfer period bits (bits [6:4] in the SCSI Transfer (SXFER) register) are set to zero and the
Extra Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1) ) is set.
Symbol Parameter
2
2. Note: for fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3) ).
Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 35 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 35 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 20 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 20 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 33 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 40
3
3. Analysis of system configuration is recommended due to reduced driver skew margin in
differential systems.
– ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 0 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 10 – ns