Avago Technologies LSI53C896 - Manual (Page 285)

PCI and External Memory Interface Timing Diagrams 6-17
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.12 PCI Configuration Register Write
Table 6.18 PCI Configuration Register Write
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
Data In
Byte Enable
Addr In
t
2
t
1
t
2
t
1
t
2
t
1
t
1
t
2
t
2
t
3
t
2
t
1
t
3
t
2
t
1
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
PAR
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C896)
STOP/
(Driven by LSI53C896)
DEVSEL/
(Driven by LSI53C896)
IDSEL
(Driven by Master)
t
1 t
2
CMD