Avago Technologies LSI53C896 - Manual (Page 308)

6-40 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.25 External Memory Read
CLK
(Driven by System)
PAR
(Driven by Master-Addr;
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C896)
STOP/
(Driven by LSI53C896)
DEVSEL/
(Driven by LSI53C896)
AD[31:0]
(Driven by Master-Addr;
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Data Driven by Memory)
1 2 3 4 5 6 7 8 9 10
LSI53C896-Data)
Addr
In
Byte Enable
LSI53C896-Data)
MAD
(Addr drvn by LSI53C896 ;
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
t
1
t
2
t
1
t
2
CMD
In
t
1
t
2
t
1
t
2
t
1
t
3
t
13
t
11 t
12
t
15