Avago Technologies LSI53C896 - Manual (Page 289)

PCI and External Memory Interface Timing Diagrams 6-21
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.16 Operating Register/SCRIPTS RAM Write, 64-Bit
Table 6.22 Operating Register/SCRIPTS RAM Write, 64-Bit
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
Byte Enable
t
2
t
1
t
2
t
1
t
2
t
1
t
2
t
2
t
3
t
2 t
1
t
3
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master)
C_BE[3:0]/
(Driven by Master)
PAR; PAR64
(Driven by Master)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C896)
STOP/
(Driven by LSI53C896)
DEVSEL/
(Driven by LSI53C896)
In In
t
1
t
2
Addr
Lo
Addr
Hi
t
1
Dual
Addr
t
1
AD[63:32]
(Driven by Master)
Hi Addr
Byte Enable
t
2
C_BE[7:4]/
(Driven by Master)
t
1
Bus CMD
t
1
t
2
Bus
CMD
In
REQ64/
(Driven by Master)
ACK64/
(Driven by LSI53C896)
Data In
t
2
t
1
t
2
t
1
Data In