Avago Technologies LSI53C896 - Manual (Page 336)

6-68 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Table 6.50 Alphanumeric List by Signal Name
A_DIFFSENS A20
A-GPIO0_
FETCH/ AB16
A_GPIO1_
MASTER/
Y16
A_GPIO2 AA16
A_GPIO3 AC17
A_GPIO4 AB17
A_SACK
−
C13
A_SACK+ A14
A_SACK2
−
B13
A_SACK2+ A13
A_SATN
−
B11
A_SATN+ B12
A_SBSY
−
C12
A_SBSY+ A12
A_SC_D
−
C15
A_SC_D+ A16
A_SD0
−
B6
A_SD0+ A6
A_SD1
−
C7
A_SD1+ B7
A_SD2
−
A7
A_SD2+ C8
A_SD3
−
D8
A_SD3+ B8
A_SD4
−
A8
A_SD4+ C9
A_SD5
−
D9
A_SD5+ B9
A_SD6
−
A9
A_SD6+ C10
A_SD7
−
D11
A_SD7+ B10
A_SD8
−
A18
A_SD8+ B18
A_SD9
−
D18
A_SD9+ C18
A_SD10
−
A19
A_SD10+ B19
A_SD11
−
D19
A_SD11+ C19
A_SD12
−
C4
A_SD12+ A3
A_SD13
−
B4
A_SD13+ A4
A_SD14
−
C5
A_SD14+ D5
A_SD15
−
B5
A_SD15+ A5
A_SDP0
−
A10
A_SDP0+ C11
A_SDP1
−
C6
A_SDP1+ D6
A_SI_O
−
B17
A_SI_O+ C17
A_SMSG
−
C14
A_SMSG+ A15
A_SREQ
−
C16
A_SREQ+ A17
A_SREQ2
−
B16
A_SREQ2+ D16
A_SRST
−
B14
A_SRST+ D13
A_SSEL
−
B15
A_SSEL+ D15
ACK64/ AB1
AD0 Y3
AD1 AA1
AD2 Y2
AD3 Y1
AD4 W3
AD5 W4
AD6 W2
AD7 W1
AD8 V4
AD9 V2
AD10 V1
AD11 U3
AD12 U2
AD13 U1
AD14 T3
AD15 T4
AD16 N3
AD17 N1
AD18 N2
AD19 M2
AD20 M3
AD21 M1
AD22 L2
AD23 L1
AD24 K2
AD25 L4
AD26 K3
AD27 J1
AD28 J2
AD29 J4
AD30 J3
AD31 H1
AD32 AC14
AD33 AA13
AD34 AC13
AD35 AB13
AD36 AB12
AD37 AA12
AD38 AC12
AD39 AB11
AD40 AC11
AD41 AA11
AD42 AC10
AD43 AB10
AD44 Y11
AD45 AA10
AD46 AC9
AD47 AB9
AD48 Y9
AD49 AA9
AD50 AC8
AD51 AB8
AD52 Y8
AD53 AA8
AD54 AC7
AD55 AB7
AD56 AA7
AD57 AC6
AD58 AB6
AD59 Y6
AD60 AA6
AD61 AC5
AD62 AB5
AD63 Y5
ALT_INTA/ F1
ALT_INTB/ G3
B_DIFFSENS Y21
B_GPIO0_
FETCH/
AA14
B_GPIO1_
MASTER/
AC15
B_GPIO2 AB15
B_GPIO3 AA15
B_GPIO4 AC16
B_SACK
−
N20
B_SACK+ P21
B_SACK2
−
P23
B_SACK2+ P22
B_SATN
−
M23
B_SATN+ N22
B_SBSY
−
N23
B_SBSY+ N21
B_SC_D
−
T20
B_SC_D+ T21
B_SD0
−
G21
B_SD0+ G22
B_SD1
−
G23
B_SD1+ H21
B_SD2
−
H20
B_SD2+ H22
B_SD3
−
H23
B_SD3+ J21
B_SD4
−
J20
B_SD4+ J22
B_SD5
−
J23
B_SD5+ K21
B_SD6
−
L20
B_SD6+ K22
B_SD7
−
K23
B_SD7+ L21
B_SD8
−
V21
B_SD8+ W23
B_SD9
−
W22
B_SD9+ W20
B_SD10
−
W21
B_SD10+ Y23
B_SD11
−
Y22
B_SD11+ AA23
B_SD12
−
D22
B_SD12+ D23
B_SD13
−
E21
B_SD13+ E20
B_SD14
−
E22
B_SD14+ E23
B_SD15
−
F21
B_SD15+ F20
B_SDP0
−
L23
B_SDP0+ L22
B_SDP1
−
F22
B_SDP1+ F23
B_SI_O
−
V22
B_SI_O+ V20
B_SMSG
−
R20
B_SMSG+ R21
B_SREQ
−
U21
B_SREQ+ V23
B_SREQ2
−
U23
B_SREQ2+ U22
B_SRST
−
R23
B_SRST+ R22
B_SSEL
−
T23
B_SSEL+ T22
C_BE0/ V3
C_BE1/ T2
C_BE2/ P1
C_BE3/ K1
C_BE4/ AC4
C_BE5/ AB4
C_BE6/ AC3
C_BE7/ AA4
CLK H3
DEVSEL/ R1
FRAME/ P2
GNT/ H4
IDSEL L3
INT_DIR G2
INTA/ F4
INTB/ F2
IRDY/ N4
MAD[0] AC23
MAD[1] AB21
MAD[2] AC22
MAD[3] AA20
MAD[4] AB20
MAD[5] AC20
MAD[6] AA19
MAD[7] Y19
MAS0/ AC18
MAS1/ AA17
MCE/ AA18
MOE/_TESTOUT Y18
MWE/ AC19
NC A1
NC A2
NC A22
NC A23
NC B1
NC B2
NC B3
NC B21
NC B22
NC B23
NC C2
NC C22
NC D21
NC AC1
NC AA22
NC AC2
NC AB2
NC AB22
NC AB23
NC AB3
PAR T1
PAR64 AA5
PERR/ R4
RBIAS M21
REQ/ H2
REQ64/ AA2
RESERVED AB14
RST/ G1
SCLK A21
SERR/ R3
STOP/ R2
TCK D1
TDI E2
TDO E1
TEST_HSC C23
TMS E3
TRDY/ P3
TEST_RST/ C1
VDD D10
VDD U20
VDD P20
VDD K20
VDD G20
VDD Y17
VDD Y14
VDD Y10
VDD Y7
VDD U4
VDD P4
VDD K4
VDD G4
VDD D17
VDD D7
VDD D14
VDD-A C20
VDD-BIAS M22
VDD-BIAS2 A11
VDD-CORE D3
VDD-CORE E4
VDD-CORE Y13
VDD-CORE AB18
VSS D20
VSS M4
VSS Y4
VSS Y12
VSS Y20
VSS M20
VSS AA3
VSS AA21
VSS D12
VSS D4
VSS K10
VSS K11
VSS K12
VSS K13
VSS K14
VSS L10
VSS L11
VSS L12
VSS L13
VSS L14
VSS C21
VSS C3
VSS M10
VSS M11
VSS M12
VSS M13
VSS M14
VSS N10
VSS N11
VSS N12
VSS N13
VSS N14
VSS P10
VSS P11
VSS P12
VSS P13
VSS P14
VSS-A B20
VSS-CORE D2
VSS-CORE Y15
VSS-CORE AB19
VSS-CORE AC21
VSS_CORE F3
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos
Signal BGA
Name Pos