Avago Technologies LSI53C896 - Manual (Page 128)

4-16 Registers
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Register: 0x3F
Max_Lat
Read Only
ML Max_Lat [7:0]
This register specifies the desired settings for latency
timer values. Max_Lat specifies how often the device
needs to gain access to the PCI bus. The value specified
in these registers is in units of 0.25 microseconds. The
LSI53C896 SCSI function sets this register to 0x40.
Register: 0x40
Capability ID
Read Only
CID Cap_ID [7:0]
This register indicates the type of data structure currently
being used. It is set to 0x01, indicating the Power
Management Data Structure.
Register: 0x41
Next Item Pointer
Read Only
NIP Next_Item_Ptr [7:0]
Bits [7:0] contain the offset location of the next item in the
function’s capabilities list. The LSI53C896 has these bits
set to zero, indicating no further extended capabilities
registers exist.
7 0
ML
0 1 0 0 0 0 0 0
7 0
CID
0 0 0 0 0 0 0 1
7 0
NIP
0 0 0 0 0 0 0 0