Avago Technologies LSI53C896 User Manual
Page 354

IX-4
Index
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
(VER[2:0])
(VUE0)
(VUE1)
(WATN)
(WIE)
(WOA)
(WRIE)
(WSR)
(WSS)
(ZMOD)
(ZSD)
Numerics
16-bit system (S16)
32/64-bit jump
32-bit addressing
3-State
64 Kbytes ROM read cycle
64-bit
addressing
addressing in SCRIPTS
SCRIPT selectors
table indirect indexing mode (64TIMOD)
8-bit/16-bit SCSI
A
A and B DIFFSENS SCSI signals
A[6:0]
A_DIFFSENS
A_GPIO0_ FETCH/
A_GPIO1_ MASTER/
A_GPIO2
A_GPIO3
A_GPIO4
A_SACK+-
A_SACK2+-
A_SATN+-
A_SBSY+-
A_SC_D+-
A_SCTRL signals
A_SD[15:0]+-
A_SDP[1:0]+-
A_SI_O+-
A_SMSG+-
A_SREQ+-
A_SREQ2+-
A_SRST+-
A_SSEL+-
aborted (ABRT)
,
absolute maximum stress ratings
AC characteristics
ACK64/
acknowledge 64
active negation
active termination
AD[63:0]
adder sum output (ADDER)
address and data signals
address/data bus
alt interrupt
A
B
ALT_INTA/
ALT_INTB/
always wide SCSI (AWS)
arbitration
in progress (AIP)
mode bits 1 and 0 (ARB[1:0])
priority encoder test (ART)
signals
assert
even SCSI parity (force bad parity) (AESP)
SATN/ on parity error (AAP)
SCSI
ACK/ signal (ACK)
,
ATN/ signal (ATN)
,
BSY/ signal (BSY)
,
C_D/ signal (C_D)
,
data bus (ADB)
I_O/ signal (I/O)
,
MSG/ signal (MSG)
REQ/ signal (REQ)
,
RST/ signal (RST)
SEL/ signal (SEL)
asynchronous SCSI
receive
send
aux_current
B
B_DIFFSENS
B_GPIO0_FETCH/
B_GPIO1_MASTER/
B_GPIO2
B_GPIO3
B_GPIO4
B_SACK+-
B_SACK2+-
B_SATN+-
B_SBSY+-
B_SC_D+-
B_SD[15:0]+-
B_SDP[1:0]+-