Avago Technologies LSI53C896 - Manual (Page 318)

6-50 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte Access Read Cycle
CLK
(Driven by System)
PAR
(Driven by LSI53C896-
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C896)
STOP/
(Driven by LSI53C896)
DEVSEL/
(Driven by LSI53C896)
AD[31:0]
(Driven by LSI53C896-
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Master-Addr; Data)
Master-Addr;-Data)
MAD
(Addr Driven by LSI53C896
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In
Addr
CMD
Byte Enable
In
Data Driven by Memory)
High Order
Address
Order
Address
Middle
Order
Address
Low