Scsi input data latch (sidl) – Avago Technologies LSI53C896 User Manual
Page 211
SCSI Registers
4-99
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
register cause the entire
word contained in SODL to be loaded into the FIFO.
These functions are summarized in the following table.
Registers: 0x50–0x51
SCSI Input Data Latch (SIDL)
Read Only
SIDL
SCSI Input Data Latch
[15:0]
This register is used primarily for diagnostic testing,
programmed I/O operation, or error recovery. Data
received from the SCSI bus can be read from this
register. Data can be written to the
register and then read
back into the LSI53C896 by reading this register to allow
loopback testing. When receiving SCSI data, the data
flows into this register and out to the host FIFO. This
register differs from the
register;
contains latched
data and the
always
contains exactly what is currently on the SCSI data bus.
Reading this register causes the SCSI parity bit to be
checked, and causes a parity error interrupt if the data is
not valid. The power-up values are indeterminate.
Register
Name
Register
Operation
FIFO Bits
FIFO Function
SODL
Write
[15:0]
Load
SODL0
Write
[7:0]
Load
SODL1
Write
[15:8]
None
15
0
SIDL
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x