Avago Technologies LSI53C896 - Manual (Page 13)

xiii
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
6.32 Slow Memory (
≥
128 Kbytes) Write Cycle 6-57
6.32 Slow Memory (
≥
128 Kbytes) Write Cycle (Cont.) 6-57
6.33
≤
64 Kbytes ROM Read Cycle 6-58
6.34
≤
64 Kbytes ROM Write Cycle 6-59
6.35 Initiator Asynchronous Send 6-60
6.36 Initiator Asynchronous Receive 6-61
6.37 Target Asynchronous Send 6-61
6.38 Target Asynchronous Receive 6-62
6.39 Initiator and Target Synchronous Transfer 6-66
6.40 LSI53C896 329 BGA (Bottom View) 6-70
6.41 LSI53C896 329 BGA Mechanical Drawing (Sheet 1 of 2) 6-71
6.41 LSI53C896 329 BGA Mechanical Drawing (Sheet 2 of 2) 6-72
B.1 16 Kbyte Interface with 200 ns Memory B-1
B.2 64 Kbyte Interface with 150 ns Memory B-2
B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with
150 ns Memory
B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4