Avago Technologies LSI53C896 User Manual
Page 38
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Functional Description
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
cache line size, but rather a multiple of the cache line size specified in
PCI 2.1 specification. The logic selects the largest multiple of the cache
line size based on the amount of data to transfer, with the maximum
allowable burst size determined from the
burst size
bits, and
, bit 2. If multiple cache line size
transfers are not desired, set the DMODE burst size to exactly the cache
line size and the chip only issues single cache line transfers.
After each data transfer, the chip re-evaluates the burst size based on the
amount of remaining data to transfer and again selects the highest
possible multiple of the cache line size, and no larger than the
burst size. The most likely scenario of this scheme
is that the chip selects the DMODE burst size after alignment, and issues
bursts of this size. The burst size is, in effect, throttled down toward the
end of a long Memory Move or Block Move transfer until only the cache
line size burst size is left. The chip finishes the transfer with this burst size.
Latency – In accordance with the PCI specification, the latency timer is
ignored when issuing a Memory Write and Invalidate command such that
when a latency time-out occurs, the LSI53C896 continues to transfer up
to a cache line boundary. At that point, the chip relinquishes the bus, and
finishes the transfer at a later time using another bus ownership. If the
chip is transferring multiple cache lines, it continues to transfer until the
next cache boundary is reached.
PCI Target Retry – During a Memory Write and Invalidate transfer, if the
target device issues a retry (STOP with no TRDY/, indicating that no data
was transferred), the chip relinquishes the bus and immediately tries to
finish the transfer on another bus ownership. The chip issues another
Memory Write and Invalidate command on the next ownership, in
accordance with the PCI specification.
PCI Target Disconnect – During a Memory Write and Invalidate
transfer, if the target device issues a disconnect the LSI53C896
relinquishes the bus and immediately tries to finish the transfer on another
bus ownership. The chip does not issue another Memory Write and
Invalidate command on the next ownership unless the address is aligned.