Avago Technologies LSI53C896 - Manual (Page 205)

SCSI Registers 4-93
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
to request data transfers. If the LSI53C896 SCSI is
functioning as a target, then the initiator has sent the
offset number of acknowledges.
SOM SCSI Synchronous Offset Maximum 0
This bit indicates that the current synchronous SREQ/,
SACK/ offset is the maximum specified by bits [3:0] in the
SCSI Transfer (SXFER) register. This bit is not latched
and may change at any time. It is used in low level
synchronous SCSI operations. When this bit is set, the
LSI53C896 SCSI is functioning as a target, and is waiting
for the initiator to acknowledge the data transfers. If the
LSI53C896 SCSI is functioning as an initiator, then the
target has sent the offset number of requests.
Register: 0x4D
SCSI Test One (STEST1)
Read/Write
SCLK SCSI Clock 7
When set, this bit disables the external SCLK
(SCSI Clock) pin, and the chip uses the PCI clock as the
internal SCSI clock. If a transfer rate of 10 Mbytes/s
(or 20 Mbytes/s on a wide SCSI bus) is desired on the
SCSI bus, this bit must be cleared and at least a 40 MHz
external SCLK must be provided.
ISO SCSI Isolation Mode 6
This bit allows the LSI53C896 SCSI function to put the
SCSI bidirectional and input pins into a low power mode
when the SCSI bus is not in use. When this bit is set, the
SCSI bus inputs are logically isolated from the SCSI bus.
R Reserved [5:4]
7 6 5 4 3 2 1 0
SCLK ISO R QEN QSEL IRM[1:0]
0 0 x x 0 0 0 0