Avago Technologies LSI53C896 - Manual (Page 58)

2-30 Functional Description
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 2.2 Parity Checking/Generation
PCI Interface**
DMA FIFO*
(64 Bits x 118)
SODL Register*
SCSI Interface**
X
S
PCI Interface**
DMA FIFO*
(64 Bits x 118)
SIDL Register*
SCSI Interface**
G
X
PCI Interface**
DMA FIFO*
(64 Bits x 118)
SODL Register*
SCSI Interface**
X
S
SODR Register*
PCI Interface**
DMA FIFO*
(64 Bits x 118)
SCSI Interface**
G
X
SCSI FIFO*
(8 or 16 Bits x 31)
X
* = No parity protection
** = Parity protected
Asynchronous
SCSI Send
Asynchronous
SCSI Receive
Synchronous
SCSI Send
Synchronous
SCSI Receive
X – Check parity
G – Generate 32-bit even PCI parity
S – Generate 8-bit odd SCSI parity