Avago Technologies LSI53C896 - Manual (Page 165)

SCSI Registers 4-53
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
•
A SCSI gross error occurs
•
An unexpected disconnect occurs
•
A SCSI reset occurs
•
A parity error is detected
•
The handshake-to-handshake timer is expired
•
The general purpose timer is expired
To determine exactly which condition(s) caused the
interrupt, read the
SCSI Interrupt Status Zero (SIST0)
and SCSI Interrupt Status One (SIST1) registers.
DIP DMA Interrupt Pending 0
This status bit is set when an interrupt condition is detected
in the DMA portion of the LSI53C896 SCSI function. The
following conditions cause a DMA interrupt to occur:
•
A PCI parity error is detected
•
A bus fault is detected
•
An abort condition is detected
•
A SCRIPTS instruction is executed in single step mode
•
A SCRIPTS interrupt instruction is executed
•
An illegal instruction is detected
To determine exactly which condition(s) caused the
interrupt, read the
DMA Status (DSTAT) register.
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
R Reserved [7:3]
FLSH Flushing 2
Reading this bit monitors if the chip is currently flushing
data. If set, the chip is flushing data from the DMA FIFO.
If cleared, no flushing is occurring. This bit is read-only,
and writes have no effect on the value of this bit.
7 3 2 1 0
R FLSH SRUN SI
x x x x x 0 0 0