Avago Technologies LSI53C896 - Manual (Page 143)

SCSI Registers 4-31
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
CCF[2:0] Clock Conversion Factor [2:0]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the SCSI core.
The synchronous portion of the SCSI core can be run at
a different clock rate for fast SCSI, using the
Synchronous Clock Conversion Factor bits. The bit
encoding is displayed in the following table. All other
combinations are reserved.
Note: It is important that these bits are set to the proper values
to guarantee that the LSI53C896 meets the SCSI timings
as defined by the ANSI specification.
SCF2
CCF2
SCF1
CCF1
SCF0
CCF0
Factor
Frequency
SCSI Clock
(MHz)
0 0 0 SCLK/3 50.01–75.0
0 0 1 SCLK/1 16.67–25.0
0 1 0 SCLK/1.5 25.01–37.5
0 1 1 SCLK/2 37.51–50.0
1 0 0 SCLK/3 50.01–75.0
1 0 1 SCLK/4 75.01–80.00
1 1 0 SCLK/6 120
1 1 1 SCLK/8 160