Avago Technologies LSI53C896 - Manual (Page 363)

Index IX-13
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
test data in 3-20
test data out 3-20
test halt SCSI clock 3-20
test interface signals 3-20
test mode select 3-20
test reset 3-20
TEST_HSC 3-20
TEST_RSTN 3-20
third dword 5-14 , 5-33 , 5-37
timer test mode (TTM) 4-98
TMS 3-20
TolerANT 1-5
enable (TE) 4-97
technology 1-5
benefits 1-6
electrical characteristics 6-8
totem pole output 3-3
transfer
control 2-25
control instructions 5-26
and SCRIPTS instruction prefetching 2-25
count 5-35
counter 5-13
information 2-20
rate synchronous 2-40
TRDY/ 2-10 , 3-7
U
Ultra SCSI
clock conversion factor bits 4-31
enable (USE) 4-30
high voltage differential transfers
20.0 Mbytes (8-bit transfers)
80 MHz clock 6-65
40.0 Mbytes (16-bit transfers)
80 MHz clock 6-65
single-ended transfers
20.0 Mbytes (8-bit transfers)
quadrupled 40 MHz clock 6-65
40.0 Mbytes (16-bit transfers)
quadrupled 40 MHz clock 6-65
Ultra2 SCSI 1-4
benefits 1-4
designing an Ultra2 SCSI system 2-23
LVDlink 2-35
synchronous data transfers 2-42
transfers
40.0 Mbytes (8-bit transfers)
quadrupled 40 MHz clock 6-66
80.0 Mbytes (16-bit transfers)
quadrupled 40 MHz clock 6-66
unexpected disconnect (UDC) 4-77 , 4-81
updated address (UA) 4-113
upper register address line (A7) 5-24
use data8/SFBR 5-23
V
VDD 3-21
-A 3-21
-Bias 3-21
-Bias2 3-21
-Core 3-21
vendor
ID (VID) 4-2
unique enhancement, bit 1 (VUE1) 4-29
unique enhancements, bit 0 (VUE0) 4-28
version (VER[2:0]) 4-17
VSS 3-21
-A 3-21
-Core 3-21
W
wait
disconnect instruction 5-18
for disconnect 2-20
for valid phase 5-32
reselect instruction 5-18
select instruction 5-16
wide SCSI
chained block moves 2-52
receive (WSR) 4-29
receive bit 2-53
send (WSS) 4-28
send bit 2-53
won arbitration (WOA) 4-45
write
read instructions 5-23
read system memory from SCRIPTS 5-35
write and invalidate 2-9 , 2-10 , 2-11 , 2-12
enable (WIE) 4-4
enable (WRIE) 4-59
WSR bit 2-53
WSS flag 2-53