Avago Technologies LSI53C896 - Manual (Page 272)

6-4 Specifications
Version 3.3 Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.2 LVD Receiver
V
CM
+
−
+
+
−
−
V
I
2
V
I
2
+
−
Table 6.5 A and B DIFFSENS SCSI Signals
Symbo
l Parameter Min Max Unit Test Conditions
V
IH
HVD sense voltage 2.4 5.0 V Note 1
V
S
LVD sense voltage 0.7 1.9 V Note 1
V
IL
SE sense voltage V
SS
−
0.3 0.5 V Note 1
I
OZ
Input leakage
−
10 10
µ
A V
PIN
= 0 V, 5.25 V
1. Functional test specified for each mode (V
IH
, V
S
, V
IL
). Refer to A_DIFFSENS and B_DIFFSENS
signal descriptions on pages 3-14 and 3-17 .
Table 6.6 Input Capacitance
Symbol Parameter Min Max Unit Test Conditions
C
I
Input capacitance of input pads – 7 pF Guaranteed by design
C
IO
Input capacitance of I/O pads – 15 pF Guaranteed by design