Figure6.32 slow memory (³ 128 kbytes) write cycle, Slow memory, 128 kbytes) write cycle – Avago Technologies LSI53C896 User Manual
Page 325
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PCI and External Memory Interface Timing Diagrams
6-57
Version 3.3
Copyright © 1998–2003 by LSI Logic Corporation. All rights reserved.
Figure 6.32 Slow Memory (
≥
128 Kbytes) Write Cycle
Figure 6.32 Slow Memory (
≥
128 Kbytes) Write Cycle (Cont.)
CLK
(Driven by System)
1
2
3
4
5
6
7
8
9
10
MAD
(Driven by LSI53C896)
High Order
Address
Middle Order
Address
Low Order
Address
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
t
13
t
11
t
12
t
24
t
25
Write
Data
Valid
t
23
t
20
CLK
(Driven by System)
11
12
13
14
15
16
17
18
19
20
MAD
(Driven by LSI53C896)
MAS1/
(Driven by LSI53C896)
MAS0/
(Driven by LSI53C896)
MCE/
(Driven by LSI53C896)
MOE/
(Driven by LSI53C896)
MWE/
(Driven by LSI53C896)
21
t
24
t
25
t
21
Valid Write Data
t
20
t
23
t
22
t
26
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