Document Outline

• Chapter 1 Overview
  • 1.1 MCF52211 Family Configurations
  • 1.2 Block Diagram
  • 1.3 Part Numbers and Packaging
  • 1.2 Features
    • 1.2.1 V2 Core Overview
    • 1.2.2 Integrated Debug Module
    • 1.2.3 JTAG
    • 1.2.4 On-Chip Memories
    • 1.2.5 Power Management
    • 1.2.6 USB On-The-Go Controller
    • 1.2.7 UARTs
    • 1.2.8 I2C Bus
    • 1.2.9 QSPI
    • 1.2.10 Fast ADC
    • 1.2.11 DMA Timers (DTIM0-DTIM3)
    • 1.2.12 General Purpose Timer (GPT)
    • 1.2.13 Periodic Interrupt Timers (PIT0 and PIT1)
    • 1.2.14 Real-Time Clock (RTC)
    • 1.2.15 Pulse-Width Modulation (PWM) Timers
    • 1.2.16 Software Watchdog Timer
    • 1.2.17 Backup Watchdog Timer
    • 1.2.18 Phase-Locked Loop (PLL)
    • 1.2.19 Interrupt Controller (INTC)
    • 1.2.20 DMA Controller
    • 1.2.21 Reset
    • 1.2.22 GPIO
• Chapter 2 Signal Descriptions
  • 2.1 Introduction
  • 2.2 Overview
  • 2.3 Pin Functions
  • 2.4 Reset Signals
  • 2.5 PLL and Clock Signals
  • 2.6 Mode Selection
  • 2.7 External Interrupt Signals
  • 2.8 Queued Serial Peripheral Interface (QSPI)
  • 2.9 I2C I/O Signals
  • 2.10 UART Module Signals
  • 2.11 DMA Timer Signals
  • 2.12 ADC Signals
  • 2.13 General Purpose Timer Signals
  • 2.14 Pulse-Width Modulator Signals
  • 2.15 Debug Support Signals
  • 2.16 EzPort Signal Descriptions
  • 2.17 Power and Ground Pins
• Chapter 3 ColdFire Core
  • 3.1 Introduction
    • 3.1.1 Overview
  • 3.2 Memory Map/Register Description
    • 3.2.1 Data Registers (D0-D7)
    • 3.2.2 Address Registers (A0-A6)
    • 3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7)
    • 3.2.4 Condition Code Register (CCR)
    • 3.2.5 Program Counter (PC)
    • 3.2.6 Vector Base Register (VBR)
    • 3.2.7 Status Register (SR)
    • 3.2.8 Memory Base Address Registers (RAMBAR, FLASHBAR)
  • 3.3 Functional Description
    • 3.3.1 Version 2 ColdFire Microarchitecture
    • 3.3.2 Instruction Set Architecture (ISA_A+)
    • 3.3.3 Exception Processing Overview
    • 3.3.4 Processor Exceptions
    • 3.3.5 Instruction Execution Timing
• Chapter 4 Multiply-Accumulate Unit (MAC)
  • 4.1 Introduction
    • 4.1.1 Overview
  • 4.2 Memory Map/Register Definition
    • 4.2.1 MAC Status Register (MACSR)
    • 4.2.2 Mask Register (MASK)
    • 4.2.3 Accumulator Register (ACC)
  • 4.3 Functional Description
    • 4.3.1 Fractional Operation Mode
    • 4.3.2 MAC Instruction Set Summary
    • 4.3.3 MAC Instruction Execution Times
    • 4.3.4 Data Representation
    • 4.3.5 MAC Opcodes
• Chapter 5 Static RAM (SRAM)
  • 5.1 Introduction
    • 5.1.1 Overview
    • 5.1.2 Features
  • 5.2 Memory Map/Register Description
    • 5.2.1 SRAM Base Address Register (RAMBAR)
  • 5.3 Initialization/Application Information
    • 5.3.1 SRAM Initialization Code
    • 5.3.2 Power Management
• Chapter 6 Clock Module
  • 6.1 Introduction
  • 6.2 Features
  • 6.3 Modes of Operation
    • 6.3.1 Backup Watchdog Timer Mode
    • 6.3.2 RTC Mode
    • 6.3.3 Normal PLL Mode
    • 6.3.4 1:1 PLL Mode
    • 6.3.5 External Clock Mode
  • 6.4 Low-Power Mode Operation
  • 6.5 Block Diagram
  • 6.6 Signal Descriptions
    • 6.6.1 EXTAL
    • 6.6.2 XTAL
    • 6.6.3 CLKOUT
    • 6.6.4 CLKMOD[1:0]
    • 6.6.5 RSTO
  • 6.7 Memory Map and Registers
    • 6.7.1 Register Descriptions
  • 6.8 Functional Description
    • 6.8.1 System Clock Modes
    • 6.8.2 Clock Operation During Reset
    • 6.8.3 System Clock Generation
    • 6.8.4 PLL Operation
• Chapter 7 Backup Watchdog Timer (BWT) Module
  • 7.1 Introduction
    • 7.1.1 Overview
    • 7.1.2 Modes of Operation
  • 7.2 Memory Map and Register Definition
    • 7.2.1 Memory Map
    • 7.2.2 Register Descriptions
  • 7.3 Functional Description
• Chapter 8 Power Management
  • 8.1 Introduction
    • 8.1.1 Features
  • 8.2 Memory Map/Register Definition
    • 8.2.1 Peripheral Power Management Registers (PPMRH, PPMRL)
    • 8.2.2 Low-Power Interrupt Control Register (LPICR)
    • 8.2.3 Peripheral Power Management Set Register (PPMRS)
    • 8.2.4 Peripheral Power Management Clear Register (PPMRC)
    • 8.2.5 Low-Power Control Register (LPCR)
  • 8.3 IPS Bus Timeout Monitor
  • 8.4 Functional Description
    • 8.4.1 Low-Power Modes
    • 8.4.2 Peripheral Behavior in Low-Power Modes
    • 8.4.3 Summary of Peripheral State During Low-Power Modes
• Chapter 9 Chip Configuration Module (CCM)
  • 9.1 Introduction
    • 9.1.1 Features
  • 9.2 External Signal Descriptions
    • 9.2.1 RCON
    • 9.2.2 CLKMOD[1:0]
    • 9.2.3 JTAG_EN
    • 9.2.4 TEST
  • 9.3 Memory Map/Register Definition
    • 9.3.1 Programming Model
    • 9.3.2 Memory Map
    • 9.3.3 Register Descriptions
• Chapter 10 Reset Controller Module
  • 10.1 Introduction
  • 10.2 Features
  • 10.3 Block Diagram
  • 10.4 Signals
    • 10.4.1 RSTI
    • 10.4.2 RSTO
  • 10.5 Memory Map and Registers
    • 10.5.1 Reset Control Register (RCR)
    • 10.5.2 Reset Status Register (RSR)
  • 10.6 Functional Description
    • 10.6.1 Reset Sources
    • 10.6.2 Reset Control Flow
    • 10.6.3 Concurrent Resets
• Chapter 11 Real-Time Clock
  • 11.1 Introduction
    • 11.1.1 Overview
    • 11.1.2 Features
    • 11.1.3 Modes of Operation
  • 11.2 Memory Map/Register Definition
    • 11.2.1 Register Descriptions
  • 11.3 Functional Description
    • 11.3.1 Prescaler and Counter
    • 11.3.2 Alarm
    • 11.3.3 Minute Stopwatch
  • 11.4 Initialization/Application Information
    • 11.4.1 Flow Chart of RTC Operation
    • 11.4.2 Code Example for Initializing the Real-Time Clock
• Chapter 12 System Control Module (SCM)
  • 12.1 Introduction
  • 12.2 Overview
  • 12.3 Features
  • 12.4 Memory Map and Register Definition
  • 12.5 Register Descriptions
    • 12.5.1 Internal Peripheral System Base Address Register (IPSBAR)
    • 12.5.2 Memory Base Address Register (RAMBAR)
    • 12.5.3 Core Reset Status Register (CRSR)
    • 12.5.4 Core Watchdog Control Register (CWCR)
    • 12.5.5 Core Watchdog Service Register (CWSR)
  • 12.6 Internal Bus Arbitration
    • 12.6.1 Overview
    • 12.6.2 Arbitration Algorithms
    • 12.6.3 Bus Master Park Register (MPARK)
  • 12.7 System Access Control Unit (SACU)
    • 12.7.1 Overview
    • 12.7.2 Features
    • 12.7.3 Memory Map/Register Definition
• Chapter 13 General Purpose I/O Module
  • 13.1 Introduction
  • 13.2 Overview
  • 13.3 Features
  • 13.4 Signal Descriptions
  • 13.5 Memory Map/Register Definition
    • 13.5.1 Ports Memory Map
  • 13.6 Register Descriptions
    • 13.6.1 Port Output Data Registers (PORTn)
    • 13.6.2 Port Data Direction Registers (DDRn)
    • 13.6.3 Port Pin Data/Set Data Registers (PORTnP/SETn)
    • 13.6.4 Port Clear Output Data Registers (CLRn)
    • 13.6.5 Pin Assignment Registers
    • 13.6.6 Pad Control Registers
  • 13.7 Ports Interrupts
• Chapter 14 Interrupt Controller Module
  • 14.1 68K/ColdFire Interrupt Architecture Overview
    • 14.1.1 Interrupt Controller Theory of Operation
  • 14.2 Memory Map
  • 14.3 Register Descriptions
    • 14.3.1 Interrupt Pending Registers (IPRHn, IPRLn)
    • 14.3.2 Interrupt Mask Register (IMRHn, IMRLn)
    • 14.3.3 Interrupt Force Registers (INTFRCHn, INTFRCLn)
    • 14.3.4 Interrupt Request Level Register (IRLRn)
    • 14.3.5 Interrupt Acknowledge Level and Priority Register (IACKLPRn)
    • 14.3.6 Interrupt Control Registers (ICRnx)
    • 14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn)
    • 14.3.8 Global Level m IACK Registers (GLmIACK)
  • 14.4 Low-Power Wakeup Operation
• Chapter 15 Universal Serial Bus, OTG Capable Controller
  • 15.1 Introduction
    • 15.1.1 USB
    • 15.1.2 USB On-The-Go
    • 15.1.3 USB-FS Features
  • 15.2 Functional Description
    • 15.2.1 Data Structures
  • 15.3 Programmers Interface
    • 15.3.1 Buffer Descriptor Table
    • 15.3.2 Rx vs. Tx as a USB Target Device or USB Host
    • 15.3.3 Addressing Buffer Descriptor Table Entries
    • 15.3.4 Buffer Descriptor Formats
    • 15.3.5 USB Transaction
  • 15.4 Memory Map/Register Definitions
    • 15.4.1 Capability Registers
  • 15.5 OTG and Host Mode Operation
  • 15.6 Host Mode Operation Examples
  • 15.7 On-The-Go Operation
    • 15.7.1 OTG Dual Role A Device Operation
    • 15.7.2 OTG Dual Role B Device Operation
    • 15.7.3 Power
    • 15.7.4 USB Suspend State
• Chapter 16 Edge Port Module (EPORT)
  • 16.1 Introduction
  • 16.2 Low-Power Mode Operation
  • 16.3 Interrupt/GPIO Pin Descriptions
  • 16.4 Memory Map/Register Definition
    • 16.4.1 EPORT Pin Assignment Register (EPPAR)
    • 16.4.2 EPORT Data Direction Register (EPDDR)
    • 16.4.3 Edge Port Interrupt Enable Register (EPIER)
    • 16.4.4 Edge Port Data Register (EPDR)
    • 16.4.5 Edge Port Pin Data Register (EPPDR)
    • 16.4.6 Edge Port Flag Register (EPFR)
• Chapter 17 DMA Controller Module
  • 17.1 Introduction
    • 17.1.1 Overview
    • 17.1.2 Features
  • 17.2 DMA Transfer Overview
  • 17.3 Memory Map/Register Definition
    • 17.3.1 DMA Request Control (DMAREQC)
    • 17.3.2 Source Address Registers (SARn)
    • 17.3.3 Destination Address Registers (DARn)
    • 17.3.4 Byte Count Registers (BCRn) and DMA Status Registers (DSRn)
    • 17.3.5 DMA Control Registers (DCRn)
  • 17.4 Functional Description
    • 17.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
    • 17.4.2 Dual-Address Data Transfer Mode
    • 17.4.3 Channel Initialization and Startup
    • 17.4.4 Data Transfer
    • 17.4.5 Termination
• Chapter 18 ColdFire Flash Module (CFM)
  • 18.1 Introduction
    • 18.1.1 Overview
    • 18.1.2 Features
  • 18.2 External Signal Description
  • 18.3 Memory Map and Register Definition
    • 18.3.1 Memory Map
    • 18.3.2 Flash Base Address Register (FLASHBAR)
    • 18.3.3 Register Descriptions
  • 18.4 Functional Description
    • 18.4.1 General
    • 18.4.2 Flash Normal Mode
    • 18.4.3 Flash Security Operation
• Chapter 19 EzPort
  • 19.1 Features
  • 19.2 Modes of Operation
  • 19.3 External Signal Description
    • 19.3.1 Overview
    • 19.3.2 Detailed Signal Descriptions
  • 19.4 Command Definition
    • 19.4.1 Command Descriptions
  • 19.5 Functional Description
  • 19.6 Initialization/Application Information
• Chapter 20 Programmable Interrupt Timers (PIT0-PIT1)
  • 20.1 Introduction
    • 20.1.1 Overview
    • 20.1.2 Block Diagram
    • 20.1.3 Low-Power Mode Operation
  • 20.2 Memory Map/Register Definition
    • 20.2.1 PIT Control and Status Register (PCSRn)
    • 20.2.2 PIT Modulus Register (PMRn)
    • 20.2.3 PIT Count Register (PCNTRn)
  • 20.3 Functional Description
    • 20.3.1 Set-and-Forget Timer Operation
    • 20.3.2 Free-Running Timer Operation
    • 20.3.3 Timeout Specifications
    • 20.3.4 Interrupt Operation
• Chapter 21 General Purpose Timer Module (GPT)
  • 21.1 Introduction
  • 21.2 Features
  • 21.3 Block Diagram
  • 21.4 Low-Power Mode Operation
  • 21.5 Signal Description
    • 21.5.1 GPT[2:0]
    • 21.5.2 GPT3
    • 21.5.3 SYNCn
  • 21.6 Memory Map and Registers
    • 21.6.1 GPT Input Capture/Output Compare Select Register (GPTIOS)
    • 21.6.2 GPT Compare Force Register (GPCFORC)
    • 21.6.3 GPT Output Compare 3 Mask Register (GPTOC3M)
    • 21.6.4 GPT Output Compare 3 Data Register (GPTOC3D)
    • 21.6.5 GPT Counter Register (GPTCNT)
    • 21.6.6 GPT System Control Register 1 (GPTSCR1)
    • 21.6.7 GPT Toggle-On-Overflow Register (GPTTOV)
    • 21.6.8 GPT Control Register 1 (GPTCTL1)
    • 21.6.9 GPT Control Register 2 (GPTCTL2)
    • 21.6.10 GPT Interrupt Enable Register (GPTIE)
    • 21.6.11 GPT System Control Register 2 (GPTSCR2)
    • 21.6.12 GPT Flag Register 1 (GPTFLG1)
    • 21.6.13 GPT Flag Register 2 (GPTFLG2)
    • 21.6.14 GPT Channel Registers (GPTCn)
    • 21.6.15 Pulse Accumulator Control Register (GPTPACTL)
    • 21.6.16 Pulse Accumulator Flag Register (GPTPAFLG)
    • 21.6.17 Pulse Accumulator Counter Register (GPTPACNT)
    • 21.6.18 GPT Port Data Register (GPTPORT)
    • 21.6.19 GPT Port Data Direction Register (GPTDDR)
  • 21.7 Functional Description
    • 21.7.1 Prescaler
    • 21.7.2 Input Capture
    • 21.7.3 Output Compare
    • 21.7.4 Pulse Accumulator
    • 21.7.5 Event Counter Mode
    • 21.7.6 Gated Time Accumulation Mode
    • 21.7.7 General-Purpose I/O Ports
  • 21.8 Reset
  • 21.9 Interrupts
    • 21.9.1 GPT Channel Interrupts (CnF)
    • 21.9.2 Pulse Accumulator Overflow (PAOVF)
    • 21.9.3 Pulse Accumulator Input (PAIF)
    • 21.9.4 Timer Overflow (TOF)
• Chapter 22 DMA Timers (DTIM0-DTIM3)
  • 22.1 Introduction
    • 22.1.1 Overview
    • 22.1.2 Features
  • 22.2 Memory Map/Register Definition
    • 22.2.1 DMA Timer Mode Registers (DTMRn)
    • 22.2.2 DMA Timer Extended Mode Registers (DTXMRn)
    • 22.2.3 DMA Timer Event Registers (DTERn)
    • 22.2.4 DMA Timer Reference Registers (DTRRn)
    • 22.2.5 DMA Timer Capture Registers (DTCRn)
    • 22.2.6 DMA Timer Counters (DTCNn)
  • 22.3 Functional Description
    • 22.3.1 Prescaler
    • 22.3.2 Capture Mode
    • 22.3.3 Reference Compare
    • 22.3.4 Output Mode
  • 22.4 Initialization/Application Information
    • 22.4.1 Code Example
    • 22.4.2 Calculating Time-Out Values
• Chapter 23 Queued Serial Peripheral Interface (QSPI)
  • 23.1 Introduction
    • 23.1.1 Block Diagram
    • 23.1.2 Overview
    • 23.1.3 Features
    • 23.1.4 Modes of Operation
  • 23.2 External Signal Description
  • 23.3 Memory Map/Register Definition
    • 23.3.1 QSPI Mode Register (QMR)
    • 23.3.2 QSPI Delay Register (QDLYR)
    • 23.3.3 QSPI Wrap Register (QWR)
    • 23.3.4 QSPI Interrupt Register (QIR)
    • 23.3.5 QSPI Address Register (QAR)
    • 23.3.6 QSPI Data Register (QDR)
    • 23.3.7 Command RAM Registers (QCR0-QCR15)
  • 23.4 Functional Description
    • 23.4.1 QSPI RAM
    • 23.4.2 Baud Rate Selection
    • 23.4.3 Transfer Delays
    • 23.4.4 Transfer Length
    • 23.4.5 Data Transfer
  • 23.5 Initialization/Application Information
• Chapter 24 UART Modules
  • 24.1 Introduction
    • 24.1.1 Overview
    • 24.1.2 Features
  • 24.2 External Signal Description
  • 24.3 Memory Map/Register Definition
    • 24.3.1 UART Mode Registers 1 (UMR1n)
    • 24.3.2 UART Mode Register 2 (UMR2n)
    • 24.3.3 UART Status Registers (USRn)
    • 24.3.4 UART Clock Select Registers (UCSRn)
    • 24.3.5 UART Command Registers (UCRn)
    • 24.3.6 UART Receive Buffers (URBn)
    • 24.3.7 UART Transmit Buffers (UTBn)
    • 24.3.8 UART Input Port Change Registers (UIPCRn)
    • 24.3.9 UART Auxiliary Control Register (UACRn)
    • 24.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
    • 24.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
    • 24.3.12 UART Input Port Register (UIPn)
    • 24.3.13 UART Output Port Command Registers (UOP1n/UOP0n)
  • 24.4 Functional Description
    • 24.4.1 Transmitter/Receiver Clock Source
    • 24.4.2 Transmitter and Receiver Operating Modes
    • 24.4.3 Looping Modes
    • 24.4.4 Multidrop Mode
    • 24.4.5 Bus Operation
  • 24.5 Initialization/Application Information
    • 24.5.1 Interrupt and DMA Request Initialization
    • 24.5.2 UART Module Initialization Sequence
• Chapter 25 I2C Interface
  • 25.1 Introduction
    • 25.1.1 Block Diagram
    • 25.1.2 Overview
    • 25.1.3 Features
  • 25.2 Memory Map/Register Definition
    • 25.2.1 I2C Address Registers (I2ADRn)
    • 25.2.2 I2C Frequency Divider Registers (I2FDRn)
    • 25.2.3 I2C Control Registers (I2CRn)
    • 25.2.4 I2C Status Registers (I2SRn)
    • 25.2.5 I2C Data I/O Registers (I2DRn)
  • 25.3 Functional Description
    • 25.3.1 START Signal
    • 25.3.2 Slave Address Transmission
    • 25.3.3 Data Transfer
    • 25.3.4 Acknowledge
    • 25.3.5 STOP Signal
    • 25.3.6 Repeated START
    • 25.3.7 Clock Synchronization and Arbitration
    • 25.3.8 Handshaking and Clock Stretching
  • 25.4 Initialization/Application Information
    • 25.4.1 Initialization Sequence
    • 25.4.2 Generation of START
    • 25.4.3 Post-Transfer Software Response
    • 25.4.4 Generation of STOP
    • 25.4.5 Generation of Repeated START
    • 25.4.6 Slave Mode
    • 25.4.7 Arbitration Lost
• Chapter 26 Analog-to-Digital Converter (ADC)
  • 26.1 Introduction
  • 26.2 Features
  • 26.3 Block Diagram
  • 26.4 Memory Map and Register Definition
    • 26.4.1 Control 1 Register (CTRL1)
    • 26.4.2 Control 2 Register (CTRL2)
    • 26.4.3 Zero Crossing Control Register (ADZCC)
    • 26.4.4 Channel List 1 and 2 Registers (ADLST1 and ADLST2)
    • 26.4.5 Sample Disable Register (ADSDIS)
    • 26.4.6 Status Register (ADSTAT)
    • 26.4.7 Limit Status Register (ADLSTAT)
    • 26.4.8 Zero Crossing Status Register (ADZCSTAT)
    • 26.4.9 Result Registers (ADRSLTn)
    • 26.4.10 Low and High Limit Registers (ADLLMTn and ADHLMTn)
    • 26.4.11 Offset Registers (ADOFSn)
    • 26.4.12 Power Control Register (POWER)
    • 26.4.13 Voltage Reference Register (CAL)
  • 26.5 Functional Description
    • 26.5.1 Input MUX Function
    • 26.5.2 ADC Sample Conversion
    • 26.5.3 ADC Data Processing
    • 26.5.4 Sequential vs. Parallel Sampling
    • 26.5.5 Scan Sequencing
    • 26.5.6 Scan Configuration and Control
    • 26.5.7 Interrupt Sources
    • 26.5.8 Power Management
    • 26.5.9 ADC Clock
    • 26.5.10 Voltage Reference Pins VREFH and VREFL
    • 26.5.11 Supply Pins VDDA and VSSA
• Chapter 27 Pulse-Width Modulation (PWM) Module
  • 27.1 Introduction
    • 27.1.1 Overview
  • 27.2 Memory Map/Register Definition
    • 27.2.1 PWM Enable Register (PWME)
    • 27.2.2 PWM Polarity Register (PWMPOL)
    • 27.2.3 PWM Clock Select Register (PWMCLK)
    • 27.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
    • 27.2.5 PWM Center Align Enable Register (PWMCAE)
    • 27.2.6 PWM Control Register (PWMCTL)
    • 27.2.7 PWM Scale A Register (PWMSCLA)
    • 27.2.8 PWM Scale B Register (PWMSCLB)
    • 27.2.9 PWM Channel Counter Registers (PWMCNTn)
    • 27.2.10 PWM Channel Period Registers (PWMPERn)
    • 27.2.11 PWM Channel Duty Registers (PWMDTYn)
    • 27.2.12 PWM Shutdown Register (PWMSDN)
  • 27.3 Functional Description
    • 27.3.1 PWM Clock Select
    • 27.3.2 PWM Channel Timers
• Chapter 28 Debug Module
  • 28.1 Introduction
    • 28.1.1 Block Diagram
    • 28.1.2 Overview
  • 28.2 Signal Descriptions
  • 28.3 Real-Time Trace Support
    • 28.3.1 Begin Execution of Taken Branch (PST = 0x5)
  • 28.4 Memory Map/Register Definition
    • 28.4.1 Shared Debug Resources
    • 28.4.2 Configuration/Status Register (CSR)
    • 28.4.3 BDM Address Attribute Register (BAAR)
    • 28.4.4 Address Attribute Trigger Register (AATR)
    • 28.4.5 Trigger Definition Register (TDR)
    • 28.4.6 Program Counter Breakpoint/Mask Registers (PBR0-3, PBMR)
    • 28.4.7 Address Breakpoint Registers (ABLR, ABHR)
    • 28.4.8 Data Breakpoint and Mask Registers (DBR, DBMR)
  • 28.5 Background Debug Mode (BDM)
    • 28.5.1 CPU Halt
    • 28.5.2 BDM Serial Interface
    • 28.5.3 BDM Command Set
  • 28.6 Real-Time Debug Support
    • 28.6.1 Theory of Operation
    • 28.6.2 Concurrent BDM and Processor Operation
  • 28.7 Processor Status, Debug Data Definition
    • 28.7.1 User Instruction Set
    • 28.7.2 Supervisor Instruction Set
  • 28.8 Freescale-Recommended BDM Pinout
• Chapter 29 IEEE 1149.1 Test Access Port (JTAG)
  • 29.1 Introduction
    • 29.1.1 Block Diagram
    • 29.1.2 Features
    • 29.1.3 Modes of Operation
  • 29.2 External Signal Description
    • 29.2.1 JTAG Enable (JTAG_EN)
    • 29.2.2 Test Clock Input (TCLK)
    • 29.2.3 Test Mode Select/Breakpoint (TMS/BKPT)
    • 29.2.4 Test Data Input/Development Serial Input (TDI/DSI)
    • 29.2.5 Test Reset/Development Serial Clock (TRST/DSCLK)
    • 29.2.6 Test Data Output/Development Serial Output (TDO/DSO)
  • 29.3 Memory Map/Register Definition
    • 29.3.1 Instruction Shift Register (IR)
    • 29.3.2 IDCODE Register
    • 29.3.3 Bypass Register
    • 29.3.4 JTAG_CFM_CLKDIV Register
    • 29.3.5 TEST_CTRL Register
    • 29.3.6 Boundary Scan Register
  • 29.4 Functional Description
    • 29.4.1 JTAG Module
    • 29.4.2 TAP Controller
    • 29.4.3 JTAG Instructions
  • 29.5 Initialization/Application Information
    • 29.5.1 Restrictions
    • 29.5.2 Nonscan Chain Operation
• Appendix A Register Memory Map Quick Reference
• Appendix B Revision History
  • B.1 Changes between Rev. 1 and Rev. 2
  • B.2 Changes between Rev. 0 and Rev. 1