Freescale Semiconductor ColdFire MCF52210 - Manual (Page 483)

Pulse-Width Modulation (PWM) Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 27-9
27.2.8 PWM Scale B Register (PWMSCLB)
PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is
generated according to the following equation:
Eqn. 27-2
Any value written to this register causes the scale counter to load the new scale value (PWMSCLB).
27.2.9 PWM Channel Counter Registers (PWMCNTn)
Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source,
PWMCLK[PCLKn]. The user can read the counters at any time without affecting the count or the
operation of the PWM channel. In left-aligned output mode, the counter counts from 0 to the value in the
period register minus 1. In center-aligned output mode, the counter counts from 0 up to the value in the
period register and then back down to 0. Therefore, given the same value in the period register,
center-aligned mode is twice the period of left-aligned mode.
Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up
for center-aligned mode, the immediate load of duty and period registers with values from the buffers, and
the output to change according to the polarity bit.
The counter is also cleared at the end of the effective period (see Section 27.3.2.5, “Left-Aligned Outputs”
and Section 27.3.2.6, “Center-Aligned Outputs” for more details). When the channel is disabled
IPSBAR
Offset:
0x1B_0009 (PWMSCLB) Access: User Read/Write
7 6 5 4 3 2 1 0
R
SCALEB
W
Reset: 0 0 0 0 0 0 0 0
Figure 27-9. PWM Scale B Register (PWMSCLB)
Table 27-9. PWMSCLB Field Descriptions
Field Description
7–0
SCALEB
Divisor used to form Clock SB from Clock B.
Clock SB
Clock B
2 PWMSCLB
×
---------------------------------------- =
SCALEB Value
0x00 256
0x01 1
0x02 2
... ...
0xFF 255