Freescale Semiconductor ColdFire MCF52210 - Manual (Page 225)

Interrupt Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 14-15
14.3.7 Software and Level m IACK Registers (SWIACKn, LmIACKn)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt
controller’s actions are very similar.
When a level-m IACK arrives in the interrupt controller, the controller examines all the currently-active
level m interrupt requests, determines the highest priority within the level, and then responds with the
unique vector number corresponding to that specific interrupt source. The vector number is supplied as the
data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller
also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved
later.
This interrupt controller design also supports the concept of a software IACK. A software IACK allows
an interrupt service routine to determine if there are other pending interrupts so that the overhead
associated with interrupt exception processing (including machine state save/restore functions) can be
minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if
there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to
the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR
register is also loaded as the software IACK is performed. If there are no active sources, the interrupt
controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also
cleared.
59 CFM CCIF SGFM command complete Cleared automatically
60 CFM PVIF Protection violation Cleared automatically
61 CFM AEIF Access error Cleared automatically
62 I 2 C1 IIF I 2 C interrupt Write IIF = 0
63 RTC RTC RTC Interrupt
See Section 11.2.1.6, “RTC Interrupt Status Register
(RTCISR) ”
IPSBAR
Offsets:
See Table 14-2 for register offsets
(SWIACKn, LmIACKn)
Access: read-only
7 6 5 4 3 2 1 0
R VECTOR
W
Reset: 0 0 0 0 0 0 0 0
Figure 14-10. Software and Level m IACK Registers (SWIACKn, LmIACKn)
Table 14-13. Interrupt Source Assignments (continued)
Source Module Flag Source Description Flag Clearing Mechanism