Freescale Semiconductor ColdFire MCF52210 - Manual (Page 516)

Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
28-20 Freescale Semiconductor
3. The execution of a HALT instruction immediately suspends execution. Attempting to execute
HALT in user mode while CSR[UHE] is cleared generates a privilege violation exception. If
CSR[UHE] is set, HALT can be executed in user mode. After HALT executes, the processor can
be restarted by serial shifting a
GO command into the debug module. Execution continues at the
instruction after HALT.
4. The assertion of the BKPT input is treated as a pseudo-interrupt; asserting BKPT creates a pending
halt postponed until the processor core samples for halts/interrupts. The processor samples for
these conditions once during the execution of each instruction; if a pending halt is detected, the
processor suspends execution and enters the halted state.
The are two special cases involving the assertion of BKPT:
• After the system reset signal is negated, the processor waits for 16 processor clock cycles before
beginning reset exception processing. If the BKPT input is asserted within eight cycles after
RESET is negated, the processor enters the halt state, signaling halt status (0xF) on the PST
outputs. While the processor is in this state, all resources accessible through the debug module can
be referenced. This is the only chance to force the processor into emulation mode through
CSR[EMU].
• After system initialization, the processor’s response to the GO command depends on the set of
BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was
loaded, the
GO command causes the processor to exit halted state and pass control to the instruction
address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the GO
command causes the processor to exit halted state and continue reset exception processing.
• The ColdFire architecture also manages a special case of BKPT asserted while the processor is
stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode
and enters the halted state, at which point all BDM commands may be exercised. When restarted,
the processor continues by executing the next sequential instruction, that is, the instruction
following the STOP opcode.
The CSR[27–24] bits indicate the halt source, showing the highest priority source for multiple halt
conditions.
28.5.2 BDM Serial Interface
When the CPU is halted and PST reflects the halt status, the development system can send unrestricted
commands to the debug module. The debug module implements a synchronous serial protocol using two
inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising
edge of the processor clock. See
Table 28-2 . The development system serves as the serial communication
channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses
full-duplex mode, where data is sent and received simultaneously by master and slave devices. The
transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown
in
Figure 28-13 , all state transitions are enabled on a rising edge of the PSTCLK clock when DSCLK is
high; DSI is sampled and DSO is driven.