1 eport pin assignment register (eppar), 1 eport pin assignment register (eppar) -3, P and register structure. refer to – Freescale Semiconductor ColdFire MCF52210 User Manual
Page 271: Table 16-2, For a description of
Edge Port Module (EPORT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
16-3
16.4.1
EPORT Pin Assignment Register (EPPAR)
The EPORT pin assignment register (EPPAR) controls the function of each pin individually.
Table 16-2. Edge Port Module Memory Map
IPSBAR
Offset
Register
Width
(bits)
Access
Reset Value
Section/Page
Supervisor Access Only Registers
1
1
User access to supervisor-only address locations have no effect and result in a bus error.
0x13_0000
EPORT Pin Assignment Register (EPPAR)
16
R/W
0x0000
0x13_0002
EPORT Data Direction Register (EPDDR)
8
R/W
0x00
0x13_0003
EPORT Interrupt Enable Register (EPIER)
8
R/W
0x00
Supervisor/User Access Registers
0x13_0004
EPORT Data Register (EPDR)
8
R/W
0xFF
0x13_0005
EPORT Pin Data Register (EPPDR)
8
R
See Section
0x13_0006
EPORT Flag Register (EPFR)
8
R/W
0x00
IPSBAR
Offset:
0x13_0000 (EPPAR)
Access: Supervisor read/write
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
EPPA7
EPPA6
EPPA5
EPPA4
EPPA3
EPPA2
EPPA1
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-2. EPORT Pin Assignment Register (EPPAR)
Table 16-3. EPPAR Field Descriptions
Field
Description
15–2
EPPAn
EPORT Pin Assignment Select Fields. The read/write EPPAn fields configure EPORT pins for level detection and
rising and/or falling edge detection.
Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request).
Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged,
the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected
to bring the device out of stop mode with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin
configured for edge detection can trigger an interrupt regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR
functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn falling edge and rising edge triggered
1–0
Reserved, must be cleared.