Freescale Semiconductor ColdFire MCF52210 - Manual (Page 241)

Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-13
15.4.1.5 OTG Interrupt Status Register (OTG_INT_STAT)
The OTG Interrupt Status Register records changes of the ID sense and VBUS signals. Software can read
this register to determine which event has caused an interrupt. Only bits that have changed since the last
software read are set. Writing a one to a bit clears the associated interrupt.
Figure 15-11 shows the
OTG_INT_STAT register.
IPSBAR
Offset:
0x1C_0010 (OTG_INT_STAT)
Access: User read/write
7 6 5 4 3 2 1 0
R
ID_CHG 1_MSEC
LINE_STATE
_CHG
Reserved
SESS_VLD
_CHG
B_SESS
_CHG
Reserved
A_VBUS
_CHG
W – –
Reset: 0 1 0 X 0 0 X 0
Figure 15-11. OTG Interrupt Status Register
Table 15-15. OTG_INT_STAT Field Descriptions
Field Description
7
ID_CHG
This bit is set when a change in the ID Signal from the USB connector is sensed.
6
1_MSEC
This bit is set when the 1 millisecond timer expires. This bit stays asserted until cleared by software. The
interrupt must be serviced every millisecond to avoid losing 1msec counts.
5
LINE_STAT
_CHG
This bit is set when the USB line state changes. The interrupt associated with this bit can be used to detect
Reset, Resume, Connect, and Data Line Pulse signals.
4
Reserved
Reserved
3
SESS_VLD
_CHG
This bit is set when a change in VBUS is detected indicating a session valid or a session no longer valid
2
B_SESS
_CHG
This bit is set when a change in VBUS is detected on a B device.
1
Reserved
Reserved
0
A_VBUS
_CHG
This bit is set when a change in VBUS is detected on an A device.