Freescale Semiconductor ColdFire MCF52210 - Manual (Page 245)

Universal Serial Bus, OTG Capable Controller
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-17
15.4.1.9 Interrupt Status Register (INT_STAT)
The Interrupt Status Register contains bits for each of the interrupt sources within the USB Module. Each
of these bits are qualified with their respective interrupt enable bits (see
Section 15.4.1.10, “Interrupt
Enable Register (INT_ENB) ”). All bits of this register are logically OR’d together along with the OTG
Interrupt Status Register (OTG_STAT) to form a single interrupt source for the ColdFire core. After an
interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit. This register
contains the value of 0x00 after a reset.
Figure 15-15 shows the INT_STAT register.
IPSBAR
Offset:
0x1C_0080 (INT_STAT)
Access: User read/write
7 6 5 4 3 2 1 0
R
STALL ATTACH RESUME SLEEP TOK_DNE SOF_TOK ERROR USB_RST
W
Reset: 0 0 0 0 0 0 0 0
Figure 15-15. Interrupt Status Register
Table 15-19. INT_STAT Field Descriptions
Field Description
7
STALL
Stall Interrupt
In Target mode this bit is asserted when a STALL handshake is sent by the SIE.
In Host mode this bit is set when the USB Module detects a STALL acknowledge during the handshake phase
of a USB transaction. This interrupt can be use to determine is the last USB transaction was completed
successfully or if it stalled.
6
ATTACH
Attach Interrupt
This bit is set when the USB Module detects an attach of a USB device. This signal is only valid if
HOST_MODE_EN is true. This interrupt signifies that a peripheral is now present and must be configured.
5
RESUME
This bit is set depending upon the DP/DM signals, and can be used to signal remote wake-up signaling on the
USB bus. When not in suspend mode this interrupt should be disabled.
4
SLEEP
This bit is set when the USB Module detects a constant idle on the USB bus for 3 milliseconds. The sleep timer
is reset by activity on the USB bus.
3
TOK_DNE
This bit is set when the current token being processed has completed. The ColdFire core should immediately
read the STAT register to determine the EndPoint and BD used for this token. Clearing this bit (by writing a one)
causes the STAT register to be cleared or the STAT holding register to be loaded into the STAT register.
2
SOF_TOK
This bit is set when the USB Module receives a Start Of Frame (SOF) token.
In Host mode this bit is set when the SOF threshold is reached, so that software can prepare for the next SOF.
1
ERROR
This bit is set when any of the error conditions within the ERR_STAT register occur. The ColdFire core must
then read the ERR_STAT register to determine the source of the error.
0
USB_RST
This bit is set when the USB Module has decoded a valid USB reset. This informs the Microprocessor that it
should write 0x00 into the address register and enable endpoint 0. USB_RST is set after a USB reset has been
detected for 2.5 microseconds. It is not asserted again until the USB reset condition has been removed and
then reasserted.