Freescale Semiconductor ColdFire MCF52210 - Manual (Page 133)

Power Management
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 8-5
8.2.2 Low-Power Interrupt Control Register (LPICR)
Implementation of low-power stop mode and exit from a low-power mode via an interrupt require
communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit
register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed
to exit a low-power mode.
NOTE
The setting of the low-power mode select (LPMD) field in the power
management module’s low-power control register (LPCR) determines
which low-power mode the device enters when a STOP instruction is issued.
If this field is set to enter stop mode, then the ENBSTOP bit in the LPICR
must also be set.
10
CDQSPI
Disable clock to the QSPI module.
0 QSPI module clock is enabled
1 QSPI module clock is disabled
9
CDI2C
Disable clock to the I2C module.
0 I2C module clock is enabled
1 I2C module clock is disabled
8
—
Reserved, should be cleared.
7
CDUART2
Disable clock to the UART2 module.
0 UART1 module clock is enabled
1 UART2 module clock is disabled
6
CDUART1
Disable clock to the UART1 module.
0 UART1 module clock is enabled
1 UART1 module clock is disabled
5
CDUART0
Disable clock to the UART0 module.
0 UART0 module clock is enabled
1 UART0 module clock is disabled
4
CDDMA
Disable clock to the DMA module.
0 DMA module clock is enabled
1 DMA module clock is disabled
3 Reserved, should be set.
2 Reserved, should be cleared.
1
CDG
Disable clock to the Global off-platform modules.
0 Global off-platform module clocks are enabled
1 Global off-platform module clocks are disabled
0 Reserved, should be cleared.
Table 8-3. PPMRL Field Descriptions (continued)
Field Description