Freescale Semiconductor ColdFire MCF52210 - Manual (Page 53)

ColdFire Core
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 3-9
Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram
The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For
sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus
(if there are no pending operand memory accesses which are assigned a higher priority). After the prefetch
address is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and
returns the instruction read data back to the IFP during the cycle. If the accessed data is not present in a
local memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in
the IC stage until the referenced data is available. As the prefetch data arrives in the IFP, it can be loaded
into the FIFO instruction buffer or gated directly into the OEP.
The V2 design uses a simple static conditional branch prediction algorithm (forward-assumed as
not-taken, backward-assumed as taken), and all change-of-flow operations are calculated by the OEP and
the target instruction address fed back to the IFP.
The IFP and OEP are decoupled by the FIFO instruction buffer, allowing instruction prefetching to occur
with the available core bus bandwidth not used for operand memory accesses. For the V2 design, the
instruction buffer contains three 32-bit locations.
Consider the operation of the OEP for three basic classes of non-branch instructions:
• Register-to-register:
op Ry,Rx
• Embedded load:
op <mem>y,Rx
• Register-to-memory (store)
move Ry,<mem>x
DSOC AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write Data
RGF