Freescale Semiconductor ColdFire MCF52210 - Manual (Page 400)

UART Modules
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
24-14 Freescale Semiconductor
NOTE
True status is provided in the UISRn regardless of UIMRn settings. UISRn
is cleared when the UART module is reset.
IPSBAR
Offset:
0x00_0214 (UISR0)
0x00_0254 (UISR1)
0x00_0294 (UISR2) Access: User read/write
7 6 5 4 3 2 1 0
R
(UISRn)
COS 0 0 0 0 DB
FFULL/
RXRDY
TXRDY
W
(UIMRn)
COS 0 0 0 0 DB
FFULL/
RXRDY
TXRDY
Reset: 0 0 0 0 0 0 0 0
Figure 24-12. UART Interrupt Status/Mask Registers (UISRn/UIMRn)
Table 24-10. UISRn/UIMRn Field Descriptions
Field Description
7
COS
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on UCTSn and was programmed in UACRn[IEC] to cause an interrupt.
6–3 Reserved, must be cleared.
2
DB
Delta break.
0 No new break-change condition to report.
Section 24.3.5, “UART Command Registers (UCRn) ,” describes the
RESET BREAK - CHANGE INTERRUPT command.
1 The receiver detected the beginning or end of a received break.
1
FFULL/
RXRDY
Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USRn[FIFO] & USRn[RXRDY]
0
TXRDY
Transmitter ready. This bit is the duplication of USRn[TXRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the
transmitter holding register when TXRDY is cleared are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.
UIMRn
[FFULL/RXRDY]
UISRn
[FFULL/RXRDY]
UMR1n[FFULL/RXRDY]
0 (RXRDY) 1 (FIFO)
0 0 Receiver not ready FIFO not full
1 0 Receiver not ready FIFO not full
0 1 Receiver is ready,
Do not interrupt
FIFO is full,
Do not interrupt
1 1 Receiver is ready,
interrupt
FIFO is full,
interrupt