Freescale Semiconductor ColdFire MCF52210 - Manual (Page 195)

MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 13-1
Chapter 13
General Purpose I/O Module
13.1 Introduction
Many of the pins associated with the external interface may be used for several different functions. When
not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In
some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.
The digital I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers
that configure, monitor, and control the port pins.
Figure 13-1 is a block diagram of the MCF52211 ports.
Figure 13-1. General Purpose I/O Module Block Diagram
DDATA[3:0] / PDD[7:4]
PORT QS
PORT AS
PORT DD
PORT UA
PORT UC
PORT TC
PORT TD
PST[3:0] / PDD[3:0]
SDA0 / PAS[1] / URXD2
SCL0 / PAS[0] / UTXD2
QSPI_CLK / PQS[2] / SCL0 / URTS1
QSPI_DIN / PQS[1] / SDA1 / URXD1
QSPI_DOUT / PQS[0] / SCL1 / UTXD1
DTIN3 / PTC[3] / DTOUT3 / PWM6
DTIN2 / PTC[2] / DTOUT2 / PWM4
DTIN1 / PTC[1] / DTOUT1 / PWM2
DTIN0 / PTC[0] / DTOUT0 / PWM0
UCTS1 / PUB[3] / SYNCA / URXD2
URTS1 / PUB[2] / SYNCB / UTXD2
URXD1 / PUB[1] / SDA1
UTXD1 / PUB[0] / SCL1
UCTS0 / PUA[3]
URTS0 / PUA[2]
URXD0 / PUA[1] / RTC_EXTAL
UTXD0 / PUA[0] / RTC_XTAL
UCTS2 / PUC[3] / SCL1
URTS2 / PUC[2] / SDA1
URXD2 / PUC[1]
UTXD2 / PUC[0]
PWM7 / PTD[3]
PWM5 / PTD[2]
PWM3 / PTD[1]
PWM1 / PTD[0]
PORT TA
GPT[3] / PTA[3] / PWM7
GPT[2] / PTA[2] / PWM5
GPT[1] / PTA[1] / PWM3
GPT[0] / PTA[0] / PWM1
PORT AN
AN0 / PAN[0]
AN1 / PAN[1]
AN2 / PAN[2]
AN3 / PAN[3]
AN4 / PAN[4]
AN5 / PAN[5]
AN6 / PAN[6]
AN7 / PAN[7]
PORT UB
QSPI_CS0 / PQS[3] / SDA0 / UCTS1
PORT NQ
IRQ1 / PNQ[1] / SYNCA / USB_ALT_CLK
IRQ2 / PNQ[2]
IRQ3 / PNQ[3]
IRQ4 / PNQ[4]
IRQ5 / PNQ[5]
IRQ6 / PNQ[6]
IRQ7 / PNQ[7]
QSPI_CS1 / PQS[4]
QSPI_CS2 / PQS[5] / SYNCB
QSPI_CS3 / PQS[6] / SYNCA