Freescale Semiconductor ColdFire MCF52210 - Manual (Page 494)

Pulse-Width Modulation (PWM) Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
27-20 Freescale Semiconductor
Eqn. 27-10
27.3.2.6.1 Center-Aligned Output Example
As an example of a center-aligned output, consider the following case:
Clock source = internal bus clock, where internal bus clock = 40 MHz (25 ns period)
PPOLn = 0, PWMPERn = 4, PWMDTYn = 1
PWMn frequency = 40 MHz / (2
×4) = 5 MHz
PWMn period = 200 ns
Shown below is the generated output waveform.
Figure 27-19. PWM Center-Aligned Output Example Waveform
27.3.2.7 PWM 16-Bit Functions
The PWM timer also has the option of generating eight 8-bit channels or four 16-bit channels for greater
PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
The PWMCTL register contains four concatenation control bits, each used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 0 and 1 are concatenated with the CON01 bit, channels 2 and
3 are concatenated with the CON23 bit, and so on. Change these bits only when both corresponding
channels are disabled.
As shown in Figure 27-20 , when channels 2 and 3 are concatenated, channel 2 registers become the high
order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers
become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel
clock select control bits (the odd numbered channel). The resulting PWM is output to the pins of the
corresponding low order 8-bit channel, as shown in
Figure 27-20 . The polarity of the resulting PWM
output is controlled by the PPOLn bit of the corresponding low order 8-bit channel as well.
After concatenated mode is enabled (PWMCTL[CONnn] bits set), enabling/disabling the corresponding
16-bit PWM channel is controlled by the low order PWMEn bit. In this case, the high order bytes’ PWMEn
bits have no effect, and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high
order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit
access to maintain data coherency.
Duty Cycle 1 PWMPOL PPOLn
[ ] PWMDTYn
PWMPERn
------------------------------- – – ⎝ ⎠
⎛ ⎞
100%
×
=
PWMn Duty Cycle 1
1
4
--- – ⎝ ⎠
⎛ ⎞
100% 75% =
×
=
DUTY CYCLE = 75%
E = 25ns
PERIOD = 200ns
E = 25ns