Freescale Semiconductor ColdFire MCF52210 User Manual
Page 509
Debug Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
28-13
DRc[4:0]: 0x07 (TDR)
Access: Supervisor write-only
BDM write-only
Second Level Trigger
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
TRC
L2EBL
L2ED
L2DI
L2EA
L2EPC L2PCI
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
First Level Trigger
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
L2T
L1T
L1EBL
L1ED
L1DI
L1EA
L1EPC L1PCI
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 28-6. Trigger Definition Register (TDR)
Table 28-9. TDR Field Descriptions
Field
Description
31–30
TRC
Trigger Response Control. Determines how the processor responds to a completed trigger condition. The trigger
response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
29
L2EBL
Enable Level 2 Breakpoint. Global enable for the breakpoint trigger.
0 Disables all level 2 breakpoints
1 Enables all level 2 breakpoint triggers
28–22
L2ED
Enable Level 2 Data Breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on
the size and placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints.
21
L2DI
Level 2 Data Breakpoint Invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a
trigger based on the occurrence of a data value other than the DBR contents.
0 No inversion
1 Invert data breakpoint comparators.
TDR Bit
Description
28
Data longword. Entire processor’s local data bus.
27
Lower data word.
26
Upper data word.
25
Lower lower data byte. Low-order byte of the low-order word.
24
Lower middle data byte. High-order byte of the low-order word.
23
Upper middle data byte. Low-order byte of the high-order word.
22
Upper upper data byte. High-order byte of the high-order word.