Freescale Semiconductor ColdFire MCF52210 - Manual (Page 103)

Clock Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-9
6.7.1.2 Synthesizer Status Register (SYNSR)
The SYNSR is a read-only register that can be read at any time. Writing to the SYNSR has no effect and
terminates the cycle normally.
5
FWKUP
Fast wakeup. Determines when the system clocks are enabled during wakeup from stop mode.
0 System clocks enabled only when PLL is locked or operating normally
1 System clocks enabled on wakeup regardless of PLL lock status
Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in stop mode, the PLL
wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. In
external clock mode, the FWKUP bit has no effect on the wakeup sequence.
4–3
—
Reserved, should be cleared.
2
CLKSRC
Clock Source. Determines whether the PLL output clock or the PLL reference clock is to drive the system
clock. This bit is ignored when the PLL is disabled, in which case the PLL reference clock drives the system
clock. Having this separate bit allows the PLL to first be enabled, and then the system clock can be switched
to the PLL output clock only after the PLL has locked. When disabling the PLL, the clock can be switched
before disabling the PLL so that a smooth transfer is ensured.
0) PLLreference clock (input clock) drives the system clock.
1) PLL output clock drives the system clock (provided the PLL is enabled).
1
PLLMODE
Determines the operating mode of the PLL. This bit should only be changed after reset with the PLL
disabled.
0) PLL operates in 1:1 mode
1) PLL operates in normal mode
0
PLLEN
Enables and disables the PLL. If the PLL is enabled out of reset, the chip does not leave the reset state until
the PLL is locked and the system clock is driven by the PLL output clock. Use the CLKSRC control bit to
switch the system clock between the PLL output clock and PLL bypass clock after the PLL is enabled.
0) PLL is disabled
1) PLL is enabled
IPSBAR
Offset: 0x12_0002 (SYNSR)
Access: Supervisor read/write
7 6 5 4 3 2 1 0
R EXTOSC OCOSC CRYOSC LOCKS LOCK LOCS — —
W
Reset: See note 1 See note 2 See note 2 0 0 0
Note: 1. Reset state determined during reset configuration.
2. See the LOCKS and LOCK bit descriptions.
Figure 6-3. Synthesizer Status Register (SYNSR)
Table 6-5. SYNCR Field Descriptions (continued)
Field Description